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PDF UJA1163TK Data sheet ( Hoja de datos )
| Número de pieza | UJA1163TK | |
| Descripción | Mini high-speed CAN system basis chip | |
| Fabricantes | NXP Semiconductors | |
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UJA1163
Mini high-speed CAN system basis chip with Standby mode
Rev. 2 — 17 April 2014
Product data sheet
1. General description
The UJA1163 is a mini high-speed CAN System Basis Chip (SBC) containing an
ISO 11898-2/5 compliant HS-CAN transceiver and an integrated 5 V/100 mA supply for a
microcontroller. The UJA1163 can be operated in a very low-current Standby mode with
bus wake-up capability and supports ISO 11898-6 compliant autonomous CAN biasing.
The UJA1163 implements the standard CAN physical layer as defined in the current
ISO11898 standard (-2 and -5). Pending the release of the updated version of ISO11898
including CAN FD, additional timing parameters defining loop delay symmetry are
included. This implementation enables reliable communication in the CAN FD fast phase
at data rates up to 2 Mbit/s.
2. Features and benefits
2.1 General
ISO 11898-2 and ISO 11898-5 compliant high-speed CAN transceiver
Loop delay symmetry timing enables reliable communication at data rates up to
2 Mbit/s in the CAN FD fast phase
Autonomous bus biasing according to ISO 11898-6
Fully integrated 5 V/100 mA low-drop voltage regulator for 5 V microcontroller
supply (V1)
Bus connections are truly floating when power to pin BAT is off
2.2 Designed for automotive applications
8 kV ElectroStatic Discharge (ESD) protection, according to the Human Body Model
(HBM) on the CAN bus pins
6 kV ESD protection, according to IEC 61000-4-2 on the CAN bus pins and on pin
BAT
CAN bus pins short-circuit proof to 58 V
Battery and CAN bus pins protected against automotive transients according to
ISO 7637-3
Very low quiescent current in Standby mode with full wake-up capability
Leadless HVSON14 package (3.0 mm 4.5 mm) with improved Automated Optical
Inspection (AOI) capability and low thermal resistance
Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)
compliant)
1 page  
NXP Semiconductors
UJA1163
Mini high-speed CAN system basis chip with Standby mode
6.1.1.2 Standby mode
Standby mode is the UJA1163’s power saving mode, offering reduced current
consumption. The transceiver is unable to transmit or receive data in Standby mode. V1
remains active in Standby mode.
The receiver monitors bus activity for a wake-up request. The bus pins are biased to GND
(via Ri(cm)) when the bus is inactive for t > tto(silence) and at approximately 2.5 V when there
is activity on the bus (autonomous biasing).
Pin RXD is forced LOW when a wake-up event is detected on the CAN bus.
The UJA1163 switches to Standby mode via Reset mode:
• from Off mode if the battery voltage rises above the power-on detection threshold
(Vth(det)pon)
• from Overtemp mode if the chip temperature falls below the overtemperature
protection release threshold, Tth(rel)otp
Standby mode can also be selected from Normal by setting pin STBN LOW.
STBN = HIGH
STANDBY
RSTN = HIGH
STBN = LOW
any reset event
NORMAL
no overtemperature
RESET
V1 undervoltage
OVERTEMP
power-on
overtemperature event
OFF
from any mode except Off
Fig 3. UJA1163 system controller state diagram
VBAT undervoltage
from any mode
UJA1163
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 April 2014
015aaa295
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 29
5 Page 
NXP Semiconductors
UJA1163
Mini high-speed CAN system basis chip with Standby mode
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(1) To prevent the bus lines being driven to a permanent dominant state, the transceiver will not switch to CAN Active mode if pin
TXD is held LOW (e.g. by a short-circuit to GND)
Fig 6. CAN transceiver state machine
6.6 CAN transceiver status pin (CTS)
Pin CTS is driven HIGH to indicate to microcontroller that the transceiver is fully enabled
and data can be transmitted and received via the TXD/RXD pins.
Pin CTS is actively driven LOW:
• while the transceiver is starting up (e.g. during a transition from Standby to Normal) or
• if pin TXD is clamped LOW for t > tto(dom)TXD or
• if an undervoltage is detected on V1
UJA1163
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 17 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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