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UJA1079ATW Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer UJA1079ATW
Beschreibung LIN core system basis chip
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
UJA1079ATW Datasheet, Funktion
UJA1079A
LIN core system basis chip
Rev. 2 — 31 January 2011
Product data sheet
1. General description
The UJA1079A core System Basis Chip (SBC) replaces the basic discrete components
commonly found in Electronic Control Units (ECU) with a Local Interconnect Network
(LIN) interface.
The UJA1079A supports the networking applications used to control power and sensor
peripherals by using the LIN interface as a local sub-bus.
The core SBC contains the following integrated devices:
LIN transceiver compliant with LIN 2.1, LIN 2.0 and SAE J2602, and compatible with
LIN 1.3
Advanced independent watchdog (UJA1079A/xx/WD versions)
250 mA voltage regulator for supplying a microcontroller; extendable with external
PNP transistor for increased current capability and dissipation distribution
Serial Peripheral Interface (SPI) (full duplex)
2 local wake-up input ports
Limp home output port
In addition to the advantages gained from integrating these common ECU functions in a
single package, the core SBC offers an intelligent combination of system-specific
functions such as:
Advanced low-power concept
Safe and controlled system start-up behavior
Detailed status reporting on system and sub-system levels
The UJA1079A is designed to be used in combination with a microcontroller. The SBC
ensures that the microcontroller always starts up in a controlled manner.






UJA1079ATW Datasheet, Funktion
NXP Semiconductors
UJA1079A
LIN core system basis chip
Table 2. Pin description …continued
Symbol
Pin
Description
WAKE1
18
local wake-up input 1
WAKE2
19
local wake-up input 2
i.c. 20 internally connected; should be left floating
i.c. 21 internally connected; should be left floating
i.c. 22 internally connected; should be left floating
GND
23 ground
i.c. 24 internally connected; should be left floating
LIN 25 LIN bus line
DLIN
26 LIN termination resistor connection
i.c. 27 internally connected; should be left floating
WBIAS
28
control pin for external wake biasing transistor
VEXCC
29
current measurement for external PNP transistor; this pin is connected to
the collector of the external PNP transistor
TEST2
30
test pin; pin should be connected to ground
VEXCTRL 31
control pin of the external PNP transistor; this pin is connected to the base
of the external PNP transistor
BAT 32 battery supply for the SBC
The exposed die pad at the bottom of the package allows for better heat dissipation from
the SBC via the printed-circuit board. The exposed die pad is not connected to any active
part of the IC and can be left floating, or can be connected to GND.
6. Functional description
The UJA1079A combines the functionality of a LIN transceiver, a voltage regulator and a
watchdog (UJA1079A/xx/WD versions) in a single, dedicated chip. It handles the
power-up and power-down functionality of the ECU and ensures advanced system
reliability. The SBC offers wake-up by bus activity, by cyclic wake-up and by the activation
of external switches. Additionally, it provides a periodic control signal for pulsed testing of
wake-up switches, allowing low-current operation even when the wake-up switches are
closed in Standby mode.
The LIN transceiver is optimized to be highly flexible with regard to bus topologies.
V1, the voltage regulator, is designed to power the ECU's microcontroller, its peripherals
and additional external transceivers. An external PNP transistor can be added to improve
heat distribution. The watchdog is clocked directly by the on-chip oscillator and can be
operated in Window, Timeout and Off modes.
6.1 System Controller
6.1.1 Introduction
The system controller manages register configuration and controls the internal functions
of the SBC. Detailed device status information is collected and presented to the
microcontroller. The system controller also provides the reset and interrupt signals.
UJA1079A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 31 January 2011
© NXP B.V. 2011. All rights reserved.
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UJA1079ATW pdf, datenblatt
NXP Semiconductors
UJA1079A
LIN core system basis chip
6.2.3 WD_and_Status register
Table 4. WD_and_Status register
Bit Symbol
Access Power-on Description
default
15:13 A2, A1, A0 R 000 register address
12 RO
R/W 0
access status
0: register set to read/write
1: register set to read only
11 WMC
R/W 0
watchdog mode control
0: Normal mode: watchdog in Window mode; Standby mode: watchdog in
Timeout mode
1: Normal mode: watchdog in Timeout mode; Standby mode: watchdog in
Off mode
10:8 NWP[1]
R/W 100
nominal watchdog period
000: 8 ms
001: 16 ms
010: 32 ms
011: 64 ms
100: 128 ms
101: 256 ms
110: 1024 ms
111: 4096 ms
7 WOS/SWR R/W -
watchdog off status/software reset
0: WDOFF pin LOW; watchdog mode determined by bit WMC
1: watchdog disabled due to HIGH level on pin WDOFF; results in software
reset
6 V1S
R-
V1 status
5 reserved R
1
0: V1 output voltage above 90 % undervoltage recovery threshold
(Vuvr; see Table 10)
1: V1 output voltage below 90 % undervoltage detection threshold
(Vuvd; see Table 10)
4 WLS1
R
-
wake-up 1 status
3 WLS2
R
-
0: WAKE1 input voltage below switching threshold (Vth(sw))
1: WAKE1 input voltage above switching threshold (Vth(sw))
wake-up 2 status
2:0 reserved R
000
0: WAKE2 input voltage below switching threshold (Vth(sw))
1: WAKE2 input voltage above switching threshold (Vth(sw))
[1] Bit NWP is set to its default value (100) after a reset.
UJA1079A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 31 January 2011
© NXP B.V. 2011. All rights reserved.
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