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UJA1066TW Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer UJA1066TW
Beschreibung High-speed CAN fail-safe system basis chip
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
UJA1066TW Datasheet, Funktion
UJA1066
High-speed CAN fail-safe system basis chip
Rev. 03 — 17 March 2010
Product data sheet
1. General description
The UJA1066 fail-safe System Basis Chip (SBC) replaces basic discrete components
which are common in every Electronic Control Unit (ECU) with a Controller Area Network
(CAN) interface. The fail-safe SBC supports all networking applications that control
various power and sensor peripherals by using high-speed CAN as the main network
interface. The fail-safe SBC contains the following integrated devices:
High-speed CAN transceiver, interoperable and downward compatible with CAN
transceiver TJA1041 and TJA1041A, and compatible with the ISO 11898-2 standard
and the ISO 11898-5 standard (in preparation)
Advanced independent watchdog
Dedicated voltage regulators for microcontroller and CAN transceiver
Serial peripheral interface (full duplex)
Local wake-up input port
Inhibit/limp-home output port
In addition to the advantages of integrating these common ECU functions in a single
package, the fail-safe SBC offers an intelligent combination of system-specific functions
such as:
Advanced low-power concept
Safe and controlled system start-up behavior
Advanced fail-safe system behavior that prevents any conceivable deadlock
Detailed status reporting on system and subsystem levels
The UJA1066 is designed to be used in combination with a microcontroller that
incorporates a CAN controller. The fail-safe SBC ensures that the microcontroller is
always started up in a defined manner. In failure situations, the fail-safe SBC will maintain
microcontroller functionality for as long as possible to provide a full monitoring and
software-driven fallback operation.
The UJA1066 is designed for 14 V single power supply architectures and for 14 V and
42 V dual power supply architectures.






UJA1066TW Datasheet, Funktion
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
Table 2. Pin description …continued
Symbol Pin Description
INH/LIMP 17 inhibit/limp-home output (BAT14 related, push-pull, default floating)
WAKE
18 local wake-up input (BAT42 related, continuous or cyclic sampling)
n.c. 19 not connected
V2 20 5 V voltage regulator output for CAN; connect a buffer capacitor to this pin
CANH
21 CANH bus line (HIGH in dominant state)
CANL
22 CANL bus line (LOW in dominant state)
GND
23 ground
SPLIT
24 CAN-bus common mode stabilization output
i.c. 25 internally connected; must be connected to pin BAT42 in the application
i.c. 26 internally connected; must be left open in the application
BAT14
27 14 V battery supply input
n.c. 28 not connected
SYSINH 29 system inhibit output; BAT42 related (e.g. for controlling external DC-to-DC
converter)
V3 30 unregulated 42 V output (BAT42 related; continuous output or Cyclic mode
synchronized with local wake-up input)
SENSE 31 fast battery interrupt / chatter detector input
BAT42
32 42 V battery supply input (connect this pin to BAT14 in 14 V applications)
The exposed die pad at the bottom of the package allows better dissipation of heat from
the SBC via the printed-circuit board. The exposed die pad is not connected to any active
part of the IC and can be left floating, or can be connected to GND for the best EMC
performance.
UJA1066_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 17 March 2010
© NXP B.V. 2010. All rights reserved.
6 of 70

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UJA1066TW pdf, datenblatt
NXP Semiconductors
UJA1066
High-speed CAN fail-safe system basis chip
Once in Start-up mode the application software has to write Operating Mode code 011 to
the Mode register within tWD(init) to initiate a transition to Flash mode. This causes a
successfully received hardware reset (handshake between the SBC and the
microcontroller) to be fed back. The transition from Start-up mode to Flash mode can only
occur once after the Flash entry sequence has been completed.
The application can choose not to enter Flash mode but instead return to Normal mode by
using the Operating Mode code 101 for handshaking. This erases the Flash mode entry
sequence.
The watchdog behavior in Flash mode is similar to its time-out behavior in Standby mode,
but Operating Mode code 111 must be used for serving the watchdog. If this code is not
used or if the watchdog overflows, the SBC will immediately force a reset and a transition
to Start-up mode. Operating Mode code 110 (leave Flash mode) is used to correctly exit
Flash mode. This results in a system reset with the corresponding reset source
information. Other Mode register codes will cause a forced reset with reset source code
‘illegal Mode register code’.
6.3 On-chip oscillator
The on-chip oscillator provides the clock signal for all digital functions and is the timing
reference for the on-chip watchdog and the internal timers.
If the on-chip oscillator frequency is too low or the oscillator is not running at all, there is
an immediate transition to Fail-safe mode. The SBC will stay in Fail-safe mode until the
oscillator has recovered to its normal frequency and the system receives a wake-up
event.
6.4 Watchdog
The watchdog provides the following timing functions:
Start-up mode; needed to give the software the opportunity to initialize the system
Window mode; detects ‘too early’ and ‘too late’ accesses in Normal mode
Time-out mode; detects a ‘too late’ access, can also be used to restart or interrupt the
microcontroller from time to time (cyclic wake-up function)
OFF mode; fail-safe shutdown during operation prevents any blind spots occurring in
the system supervision
The watchdog is clocked directly by the on-chip oscillator.
To guarantee fail-safe control of the watchdog via the SPI, all watchdog accesses are
coded with redundant bits. Therefore, only certain codes are allowed for a proper
watchdog service.
UJA1066_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 17 March 2010
© NXP B.V. 2010. All rights reserved.
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