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24FC1026 Schematic ( PDF Datasheet ) - Microchip

Teilenummer 24FC1026
Beschreibung EEPROM
Hersteller Microchip
Logo Microchip Logo 




Gesamt 30 Seiten
24FC1026 Datasheet, Funktion
24AA1026/24LC1026/24FC1026
1024K I2C Serial EEPROM
Device Selection Table
Part
Number
VCC
Range
Max. Clock Temp.
Frequency Ranges
24AA1026
24LC1026
24FC1026
1.7V-5.5V
2.5V-5.5V
1.8V-5.5V
400 kHz(1)
400 kHz(2)
1 MHz(3)
I
I, E
I
Note 1: 100 kHz for VCC < 2.5V
2: 100 kHz for VCC < 4.5V (E-temp)
3: 400 kHz for VCC < 2.5V
Features
• Low-Power CMOS Technology:
- Read current 450 µA, maximum
- Standby current 5 µA, maximum
• 2-Wire Serial Interface, I2C Compatible
• Cascadable up to Four Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• 1 MHz Clock for FC Versions
• Page Write Time 3 ms, typical
• Self-Timed Erase/Write Cycle
• 128-Byte Page Write Buffer
• Hardware Write-Protect
• Electrostatic Discharge (ESD) Protection >4000V
• More than One Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• Packages Include 8-lead PDIP, SOIC and SOIJ
• RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40C to +85C
- Automotive (E): -40C to +125C
Description
The Microchip Technology Incorporated
24AA1026/24LC1026/24FC1026 (24XX1026*) is a
128K x 8 (1024 Kbit) Serial Electrically Erasable
PROM, capable of operation across a broad voltage
range (1.7V to 5.5V).
It has been developed for advanced, low-power
applications such as personal communications or data
acquisition. This device has both byte write and page
write capability of up to 128 bytes of data.
This device is capable of both random and sequential
reads. Reads may be sequential within address
boundaries 0000h to FFFFh and 10000h to 1FFFFh.
Functional address lines allow up to four devices on the
same data bus. This allows for up to 4 Mbits total
system EEPROM memory. This device is available in
the standard 8-pin PDIP, SOIC and SOIJ packages.
Package Type
8-Lead PDIP
8-Lead SOIC/SOIJ
NC 1
A1 2
A2 3
VSS 4
8 VCC NC
7 WP A1
6 SCL A2
5 SDA VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
Block Diagram
A1A2 WP
HV Generator
I/O
Control
Logic
Memory
Control
Logic
I/O SCL
SDA
VCC
VSS
XDEC
EEPROM
Array
Page Latches
YDEC
Sense AMP
R/W Control
*24XX1026 is used in this document as a generic part
number for the 24AA1026/24LC1026/24FC1026
devices.
2011-2015 Microchip Technology Inc.
DS20002270E-page 1






24FC1026 Datasheet, Funktion
24AA1026/24LC1026/24FC1026
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name
NC
A1
A2
VSS
SDA
SCL
WP
VCC
PIN FUNCTION TABLE
PDIP
SOIC
SOIJ
11
22
33
44
55
66
77
88
1
2
3
4
5
6
7
8
Function
Not Connected
User Configurable Chip Select
User Configurable Chip Select
Ground
Serial Data
Serial Clock
Write-Protect Input
+1.7 to 5.5V (24AA1026)
+2.5 to 5.5V (24LC1026)
+1.8 to 5.5V (24FC1026)
2.1 A1, A2 Chip Address Inputs
The A1 and A2 inputs are used by the 24XX1026 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the comparison is true.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. In most
applications, the chip address inputs A1 and A2 are
hard-wired to logic ‘0’ or logic ‘1’. For applications in
which these pins are controlled by a microcontroller or
other programmable device, the chip address pins
must be driven to logic ‘0’ or logic ‘1’ before normal
device operation can proceed.
3.0 FUNCTIONAL DESCRIPTION
The 24XX1026 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX1026 works as a slave. Both master and slave
can operate as a transmitter or receiver, but the master
device determines which mode is activated.
2.2 Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an
open-drain terminal, therefore, the SDA bus requires a
pull-up resistor to VCC (typical 10 kfor 100 kHz, 2 k
for 400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.3 Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
2.4 Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited, but read operations are
not affected.
DS20002270E-page 6
2011-2015 Microchip Technology Inc.

6 Page









24FC1026 pdf, datenblatt
24AA1026/24LC1026/24FC1026
8.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
control byte is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1 Current Address Read
The 24XX1026 contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous read access was to address n (n is any legal
address), the next current address read operation
would access data from address n + 1.
Upon receipt of the control byte with R/W bit set to one,
the 24XX1026 issues an acknowledge and transmits
the 8-bit data word. The master will not acknowledge
the transfer, but does generate a Stop condition and the
24XX1026 discontinues transmission (Figure 8-1).
FIGURE 8-1:
CURRENT ADDRESS
READ
Bus Activity
Master
SDA Line
Bus Activity
S
T
A Control
R Byte
T
S
10
10
AAB
210
1
A
C
K
Data
Byte
S
T
O
P
P
N
O
A
C
K
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24XX1026 as part of a write operation (R/W bit set to
‘0’). After the word address is sent, the master
generates a Start condition following the acknowledge.
This terminates the write operation, but not before the
internal Address Pointer is set. Then, the master issues
the control byte again, but with the R/W bit set to a one.
The 24XX1026 will then issue an acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition which causes the 24XX1026 to discontinue
transmission (Figure 8-2). After a random Read
command, the internal address counter will point to the
address location following the one that was just read.
8.3 Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24XX1026 transmits
the first data byte, the master issues an acknowledge
as opposed to the Stop condition used in a random
read. This acknowledge directs the 24XX1026 to
transmit the next sequentially addressed 8-bit word
(Figure 8-3). Following the final byte transmitted to the
master, the master will NOT generate an acknowledge,
but will generate a Stop condition. To provide
sequential reads, the 24XX1026 contains an internal
Address Pointer which is incremented by one at the
completion of each operation. This Address Pointer
allows half the memory contents to be serially read
during one operation. Sequential read address
boundaries are 00000h to 0FFFFh and 10000h to
1FFFFh. The internal Address Pointer will
automatically roll over from address 0FFFFh to
address 00000h if the master acknowledges the byte
received from the array address, 0FFFFh. The internal
address counter will automatically roll over from
address 1FFFFh to address 10000h if the master
acknowledges the byte received from the array
address 1FFFFh.
DS20002270E-page 12
2011-2015 Microchip Technology Inc.

12 Page





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