24AA08H Datasheet PDF - Microchip
| Part Number | 24AA08H | |
| Description | EEPROM | |
| Manufacturers | Microchip | |
| Logo |  |
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There is a preview and 24AA08H download ( pdf file ) link at the bottom of this page. Total 30 Pages | ||
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24AA08H/24LC08BH
8K I2C™ Serial EEPROM with Half-Array Write-Protect
Device Selection Table
Part
Number
VCC
Range
Max. Clock
Frequency
24AA08H
1.7-5.5
400 kHz(1)
24LC08BH 2.5-5.5
400 kHz
Note 1: 100 kHz for VCC <2.5V
Temp.
Ranges
I
I, E
Features:
• Single Supply with Operation Down to 1.7V for
24AA08H Devices, 2.5V for 24LC08BH Devices
• Low-Power CMOS Technology:
- Read current 1 mA, max.
- Standby current 1 A, max.
• 2-Wire Serial Interface, I2C™ Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 3 ms, typical
• Self-Timed Erase/Write Cycle
• 16-Byte Page Write Buffer
• Hardware Write-Protect for Half-Array (200h-3FFh)
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 years
• Factory Programming available
• Packages include 8-lead PDIP, SOIC, TSSOP,
TDFN, MSOP and 5-lead SOT-23
• RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
*24XX08H is used in this document as a generic part
number for the 24AA08H/24LC08BH devices.
Description:
The Microchip Technology Inc. 24AA08H/24LC08BH
(24XX08H*) is an 8 Kbit Electrically Erasable PROM.
The device is organized as four blocks of 256 x 8-bit
memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.7V, with standby
and active currents of only 1 A and 1 mA,
respectively. The 24XX08H also has a page write
capability for up to 16 bytes of data. The 24XX08H is
available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, 2x3 TDFN and MSOP packages, and
is also available in the 5-lead SOT-23 package. All
packages are RoHS compliant.
Block Diagram
WP
HV
Generator
I/O
Control
Logic
I/O
SCL
SDA
VCC
VSS
Memory
Control
Logic
XDEC
EEPROM
Array
Page
Latches
YDEC
Sense Amp.
R/W Control
Package Types
PDIP, MSOP
SOIC, TSSOP
A0 1
A1 2
A2 3
VSS 4
8 VCC A0
7 WP A1
6 SCL A2
5 SDA VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
SOT-23-5
TDFN
SCL
Vss
SDA
1
2
3
5 WP
4 Vcc
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
Note:
Pins A0, A1 and A2 are not used by the 24XX08. (No
internal connections).
2008-2013 Microchip Technology Inc.
DS20002084B-page 1
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24AA08H/24LC08BH
2.0 FUNCTIONAL DESCRIPTION
The 24XX08H supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX08H works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1 Bus Not Busy (A)
Both data and clock lines remain high.
3.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first-in first-
out (FIFO) fashion.
3.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Note:
The 24XX08H does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX08H) will leave the data
line high to enable the master to generate the Stop
condition.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
SCL
(B)
(D)
(D)
(C) (A)
SDA
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
2008-2013 Microchip Technology Inc.
DS20002084B-page 5
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 24AA08H electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ 24AA08H.PDF Datasheet ] | |
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