Datenblatt-pdf.com


11AA02UID Schematic ( PDF Datasheet ) - Microchip

Teilenummer 11AA02UID
Beschreibung EEPROM
Hersteller Microchip
Logo Microchip Logo 




Gesamt 30 Seiten
11AA02UID Datasheet, Funktion
11AA02UID
2K UNI/O® Serial EEPROM with Unique 32-Bit Serial Number
DEVICE SELECTION TABLE
Part Number
Density
(bits)
VCC Range
11AA02UID
2K
1.8-5.5V
Page Size
(Bytes)
16
Temp.
Ranges
I
Packages
SN, TT
Unique ID
Length
32-Bit
Features:
• Preprogrammed 32-Bit Serial Number:
- Unique across all UID-family EEPROMs
- Scalable to 48-bit, 64-bit, 128-bit, 256-bit,
and other lengths
• Single I/O, UNI/O® Serial Interface Bus
• Low-Power CMOS Technology:
- 1 mA active current, typical
- 1 µA standby current (max.)
• 256 x 8 Bit Organization
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kbps Max. Bit Rate – Equivalent to 100 kHz
Clock Frequency
• Self-Timed Write Cycle (including Auto-Erase)
• Page-Write Buffer for up to 16 Bytes
• STATUS Register for Added Control:
- Write enable latch bit
- Write-In-Progress bit
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-in Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
• High Reliability:
- Endurance: 1,000,000 erase/write cycles
- Data retention: > 200 years
- ESD protection: > 4,000V
• 3-Lead SOT-23 and 8-Lead SOIC Packages
• RoHS Compliant
• Available Temperature Ranges:
- Industrial (I): -40°C to +85°C
Description:
The Microchip Technology Inc. 11AA02UID device is a
2 Kbit Serial Electrically Erasable PROM with a
preprogrammed, 32-bit unique ID. The device is
organized in blocks of x8-bit memory and support the
patented* single I/O UNI/O® serial bus. By using
Manchester encoding techniques, the clock and data
are combined into a single, serial bit stream (SCIO),
where the clock signal is extracted by the receiver to
correctly decode the timing and value of each bit.
Low-voltage design permits operation down to 1.8V,
with standby and active currents of only 1 uA and 1 mA,
respectively.
The 11AA02UID is available in standard 8-lead SOIC
and 3-lead SOT-23 packages.
Package Types (not to scale)
SOT23
(TT)
VSS 3
2 VCC
1 SCIO
SOIC
(SN)
NC
NC
NC
VSS
1
2
3
4
8 VCC
7 NC
6 NC
5 SCIO
Pin Function Table
Name
Function
SCIO
VSS
VCC
Serial Clock, Data Input/Output
Ground
Supply Voltage
* Microchip’s UNI/O® Bus products are covered by the following patents issued in the U.S.A.: 7,376,020 and 7,788,430.
2013 Microchip Technology Inc.
DS20005206A-page 1






11AA02UID Datasheet, Funktion
11AA02UID
3.0 BUS CHARACTERISTICS
3.1 Standby Pulse
When the master has control of SCIO, a standby pulse
can be generated by holding SCIO high for TSTBY. At
this time, the 11AA02UID will reset and return to
Standby mode. Subsequently, a high-to-low transition
on SCIO (the first low pulse of the header) will return
the device to the active state.
Once a command is terminated satisfactorily (i.e., via
a NoMAK/SAK combination during the Acknowledge
sequence), performing a standby pulse is not required
to begin a new command as long as the device to be
selected is the same device selected during the previ-
ous command. However, a period of TSS must be
observed after the end of the command and before the
beginning of the start header. After TSS, the start
header (including THDR low pulse) can be transmitted
in order to begin the new command.
If a command is terminated in any manner other than a
NoMAK/SAK combination, then the master must
perform a standby pulse before beginning a new
command, regardless of which device is to be selected.
Note:
After a POR/BOR event occurs, a low-to-
high transition on SCIO must be gener-
ated before proceeding with communica-
tion, including a standby pulse.
An example of two consecutive commands is shown in
Figure 3-1. Note that the device address is the same
for both commands, indicating that the same device is
being selected both times.
A standby pulse cannot be generated while the slave
has control of SCIO. In this situation, the master must
wait for the slave to finish transmitting and to release
SCIO before the pulse can be generated.
If, at any point during a command an error is detected
by the master, a standby pulse should be generated
and the command should be performed again.
FIGURE 3-1:
CONSECUTIVE COMMANDS EXAMPLE
SCIO
Standby Pulse(1)
Start Header
01010101
Device Address
10100000
SCIO
Start Header
01010101
Device Address
10100000
Note 1: After a POR/BOR event, a low-to-high transition on SCIO is required to occur before the first
standby pulse.
3.2 Start Data Transfer
All operations must be preceded by a start header. The
start header consists of holding SCIO low for a period
of THDR, followed by transmitting an 8-bit ‘01010101
code. This code is used to synchronize the slave’s
internal clock period with the master’s clock period, so
accurate timing is very important.
FIGURE 3-2:
START HEADER
When a standby pulse is not required (i.e., between
successive commands to the same device), a period of
TSS must be observed after the end of the command
and before the beginning of the start header.
Figure 3-2 shows the waveform for the start header,
including the required Acknowledge sequence at the
end of the byte.
SCIO
TSS THDR Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ Data ‘0’ Data ‘1’ MAK NoSAK
DS20005206A-page 6
2013 Microchip Technology Inc.

6 Page









11AA02UID pdf, datenblatt
11AA02UID
4.4 Write Enable (WREN) and Write
Disable (WRDI) Instructions
The 11AA02UID contains a write enable latch. See
Table 6-1 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI instruction will reset the latch.
Note:
The WREN and WRDI instructions must be
terminated with a NoMAK following the
command byte. If a NoMAK is not
received at this point, the command will be
considered invalid, and the device will go
into Idle mode without responding with a
SAK or executing the command.
The following is a list of conditions under which the
write enable latch will be reset:
• Power-up
WRDI instruction successfully executed
WRSR instruction successfully executed
WRITE instruction successfully executed
ERAL instruction successfully executed
SETAL instruction successfully executed
FIGURE 4-4:
WRITE ENABLE COMMAND SEQUENCE
SCIO
Standby Pulse
Start Header
01010101
Device Address
10100000
SCIO
Command
10010110
FIGURE 4-5:
WRITE DISABLE COMMAND SEQUENCE
SCIO
Standby Pulse
Start Header
01010101
Device Address
10100000
SCIO
Command
10010001
DS20005206A-page 12
2013 Microchip Technology Inc.

12 Page





SeitenGesamt 30 Seiten
PDF Download[ 11AA02UID Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
11AA02UIDEEPROMMicrochip
Microchip

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche