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K4D261638K-LC50 Schematic ( PDF Datasheet ) - Samsung

Teilenummer K4D261638K-LC50
Beschreibung 128Mbit GDDR SDRAM
Hersteller Samsung
Logo Samsung Logo 




Gesamt 18 Seiten
K4D261638K-LC50 Datasheet, Funktion
K4D261638K
128M GDDR SDRAM
128Mbit GDDR SDRAM
2M x 16Bit x 4 Banks
Graphic Double Data Rate
Synchronous DRAM
Revision 1.3
July 2007
Notice
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
- 1 /19 -
Rev. 1.3 July 2007






K4D261638K-LC50 Datasheet, Funktion
K4D261638K
6.0 BLOCK DIAGRAM (2Mbit x 16I/O x 4 Bank)
128M GDDR SDRAM
CK,CK
ADDR
Bank Select
CK, CK
16
Intput Buffer
Data Input Register
Serial to parallel
LWE
LDMi
2Mx16
2Mx16
2Mx16
2Mx16
32 16
x16
DQi
Column Decoder
Latency & Burst Length
LCKE
LRAS LCBR LWE
LCAS
Programming Register
LWCBR
Timing Register
DLL
CK,CK
LDMi
Data Strobe
CK,CK CKE CS RAS CAS WE LDM UDM
- 6 /19 -
Rev. 1.3 July 2007

6 Page









K4D261638K-LC50 pdf, datenblatt
K4D261638K
128M GDDR SDRAM
9.3 AC INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS=0V, VDD=2.5V+ 5%, VDDQ=2.5V+ 5%,TA=0 to 65°C)
Parameter
Symbol
Min
Typ
Max
Input High (Logic 1) Voltage; DQ
VIH VREF+0.35
-
-
Input Low (Logic 0) Voltage; DQ
VIL -
- VREF-0.35
Clock Input Differential Voltage; CK and CK VID 0.7
- VDDQ+0.6
Clock Input Crossing Point Voltage; CK and CK
VIX 0.5*VDDQ-0.2 - 0.5*VDDQ+0.2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input level on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
3. For K4D261638J-LC50, VDD & VDDQ = 2.375V to 2.7V.
Unit
V
V
V
V
Note
1
2
9.4 AC OPERATING TEST CONDITIONS
(VDD=2.5V+ 5%*2 , TA= 0 to 65°C)
Parameter
Value
Unit Note
Input reference voltage for CK(for single ended)
CK and CK signal maximum peak swing
0.50*VDDQ
1.5
V1
V
CK signal minimum slew rate
1.0 V/ns
Input Levels(VIH/VIL)
Input timing measurement reference level
Output timing measurement reference level
Output load condition
VREF+0.35/VREF-0.35
VREF
Vtt
See Fig.1
V
V
V
Note :
1. In case of differential clocks(CK and CK ), input reference voltage for clock is a CK and CK’s crossing point.
2. For K4D261638J-LC50, VDD & VDDQ = 2.375V to 2.7V.
Vtt=0.5*VDDQ
Output
Z0=50
CLOAD=30pF
RT=50
VREF
=0.5*VDDQ
(Fig. 1) Output Load Circuit
- 12 /19 -
Rev. 1.3 July 2007

12 Page





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