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PDF CD4034 Data sheet ( Hoja de datos )
| Número de pieza | CD4034 | |
| Descripción | CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register | |
| Fabricantes | SYC | |
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CD4034
CMOS 8-Stage Static Bidirectional Parallel/Serial
Input/Output Bus Register
Features
Description
• High Voltage Types (20V Rating)
• Bidirectional Parallel Data Input
• Parallel or Serial Inputs/Parallel Outputs
• Asynchronous or Synchronous Parallel Data Loading
• Parallel Data-Input Enable on “A” Data Lines (3-State
Output)
• Data Recirculation for Register Expansion
• Multipackage Register Expansion
• Fully Static Operation DC-to-10MHz (typ.) at
VDD = 10V
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full
Package-Temperature Range;
- 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Parallel Input/Parallel Output, Serial Input/Parallel Out-
put, Serial Input/Serial Output Register
• Shift Right/Shift Left Register
• Shift Right/Shift Left With Parallel Loading
• Address Register
• Buffer Register
• Bus System Register with Enable Parallel Lines at Bus
Side
• Double Bus Register System
• Up-Down Johnson or Ring Counter
• Pseudo-Random Code Generators
• Sample and Hold Register (Storage, Counting,
Display)
• Frequency and Phase Comparator
CD4034BMS is a static eight-stage parallel-or serial-input
parallel-output register. It can be used to:
1) bidirectionally transfer parallel information between two
buses, 2) convert serial data to parallel form and direct the
parallel data to either of two buses, 3) store (recirculate) par-
allel data, or 4) accept parallel data from either of two buses
and convert that data to serial form. Inputs that control the
operations include a single-phase CLOCK (CL), A DATA
ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/S),
A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B), and PARAL-
LEL/SERIAL (P/S).
Data inputs include 16 bidirectional parallel data lines of
which the eight A data lines are inputs (3-state outputs) and
the B data lines are outputs (inputs) depending on the signal
level on the A/B input. In addition, an input for SERIAL DATA
is also provided.
All register stages are D-type master-slave flip-flops with
separate master and slave clock inputs generated internally
to allow synchronous or asynchronous data transfer from
master to slave. Isolation from external noise and the effects
of loading is provided by output buffering.
Pinout
CD4034BMS
TOP VIEW
81
72
63
54
45
36
27
18
“A” ENABLE 9
SERIAL INPUT 10
A/B 11
VSS 12
24 VDD
23 8
22 7
21 6
20 5
19 4
18 3
17 2
16 1
15 CLOCK
14 A/S
13 P/S
www.sycelectronica.com.ar
1 page  
Specifications CD4034BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V
Input Voltage Low
Input Voltage High
Propagation Delay
Parallel In to Parallel Out
Propagation Delay
Serial to Parallel Out
Propagation Delay 3-State
AE to Out ‘A’
Propagation Delay 3-State
AE to Out ‘A’
Transition Time
Maximum Clock Input
Frequency
Minimum Data Setup
Time
Serial Data to Clock
Minimum Data Setup
Time Parallel Data to
Clock
Minimum Clock Pulse
Width
Maximum Clock Rise and
Fall Time (Note 5)
Minimum High Level
Pulse Width AE, P/S, A/S
Input Capacitance
VIL
VIH
TPHL
TPLH
TPHL
TPLH
TPLZ
TPHZ
TPZL
TPZH
TTLH
TTHL
FCL
TS
TS
TW
TRCL
TFCL
TW
CIN
VDD = 10V, VOH > 9V,
VOL < 1V
VDD = 10V, VOH > 9V,
VOL < 1V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
Any Input
NOTES
1, 2
1, 2
1, 2
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
TEMPERATURE
+125oC
-55oC
+25oC, +125oC,
-55oC
+25oC, +125oC,
-55oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
MIN
-
-
-
+7
-
-
700
-
-
-
-
-
-
-
-
5
7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX
-2.4
-4.2
3
UNITS
mA
mA
V
-V
240 ns
170 ns
- ns
240 ns
170 ns
160 ns
120 ns
160 ns
120 ns
100 ns
80 ns
- MHz
- MHz
160 ns
60 ns
40 ns
50 ns
30 ns
20 ns
250 ns
100 ns
70 ns
15 µs
15 µs
15 µs
350 ns
140 ns
80 ns
7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
5. If more than one unit is cascaded, tRCL should be made less than or equal to the sum of the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
www.sycelectronica.com.ar
5 Page 
CD4034BMS
VSS
PROTECTION NETWORK
ON ALL “A” AND “B”
DATA INPUTS
K
p
n
K
P/S CLM
An
CLS
1 OF 8 STAGES
M
Q’ Q’
VDD
SERIAL
DATA
VDD
Dp
n
P/S
p
n
CLM
CLM
p
n
p
n
CLS
CLS
p
n
L CLM
CLS
VSS
PROTECTION NETWORK
ON SERIAL DATA INPUT
p
n
L Bn
FIGURE 11. REGISTER STAGE LOGIC DIAGRAM (1 OF 8 STAGES)
M VSS
N VDD
Q’
N VSS
Q (TO NEXT STAGE D)
TRUTH TABLE REGISTER INPUT-LEVELS AND
RESULTING REGISTER OPERATION
“A”
ENABLE P/S A/B A/S
OPERATION*
0 0 0 X Serial Mode; Synch. Serial Data Input, “A” Parallel Data Outputs Disabled
0 0 1 X Serial Mode; Synch. Serial Data Input, “B” Parallel Data Output
0 1 0 0 Parallel Mode; “B” Synch. Parallel Data Inputs, “A” Parallel Data Outputs Disabled
0 1 0 1 Parallel Mode; “B” Asynch. Parallel Data Inputs, “A” Parallel Data Outputs Disabled
0 1 1 0 Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data Outputs, Synch. Data
Recirculation
0 1 1 1 Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data Outputs, Asynch. Data
Recirculation
1 0 0 X Serial Mode; Synch. Serial Data Input, “A” Parallel Data Output
1 0 1 X Serial Mode; Synch. Serial Data Input, “B” Parallel Data Output
1 1 0 0 Parallel Mode; “B” Synch. Parallel Data Input, “A” Parallel Data Output
1 1 0 1 Parallel Mode; “B” Asynch. Parallel Data Input, “A” Parallel Data Output
1 1 1 0 Parallel Mode; “A” Synch, Parallel Data Input, “B” Parallel Data Output
1 1 1 1 Parallel Mode; “A” Asynch. Parallel Data Input, “B” Parallel Data Output
*Outputs change at positive transition of clock in the serial mode and when the A/S control input is “low” in the parallel mode. During
transfer from parallel to serial operation A/S should remain low in order to prevent DS transfer into Flip Flops.
1 = High Level
0 = Low Level
X = Don’t Care
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11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CD4034.PDF ] | |
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