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CH7002D-V Schematic ( PDF Datasheet ) - ETC

Teilenummer CH7002D-V
Beschreibung Scalable VGA to NTSC/PAL Encoder
Hersteller ETC
Logo ETC Logo 




Gesamt 36 Seiten
CH7002D-V Datasheet, Funktion
CHRONTEL
CH7002D
Preliminary
Scalable VGA to NTSC/PAL Encoder
Features
• Fully integrated solution for PC to TV display
• TrueScale TM rendering engine supports underscan
operation for both 640x480 or 800x600 inputs
• Advanced 3-line digital flicker filtering with
programmable algorithm selections
• Fully programmable through I2C port or hardware
(pin-based) controls
• Wide range of VGA software drivers for full
synchronization and image positioning
• Auto-detection of TV presence
• Programmable power management features three
power-down modes
• Supports both NTSC and PAL (B, D, G, H, or I) TV
formats onto both composite and S-Video
• Triple 8-bit ADC inputs and triple 8-bit DAC outputs
• On-chip reference generation and loop filter
• Offered in 44-pin PLCC package
General Description
Chrontel’s CH7002 VGA to NTSC/PAL encoder is a stand-
alone integrated circuit which provides a PC 99 compliant
solution for TV output. It accepts RGB analog inputs directly
from VGA controllers and converts them directly into NTSC
or PAL TV format, with simultaneous composite and
S-Video outputs.
This circuit integrates a digital NTSC/PAL encoder with 8-
bit ADC and DAC interfaces, a 3-line vertical filter, and low-
jitter phase-locked loop to create outstanding quality video.
Through Chrontel’s TrueScale TM rendering technology, the
CH7002 supports full vertical and horizontal underscan
operation from either 640x480 or 800x600 input to either
NTSC or PAL outputs.
A high level of performance along with full programmability
makes the CH7002 ideal for system-level PC or Web
browser solutions. All features are software programmable,
through a standard I2C port, to enable fully integrated system
solutions by using a TV as the primary display device.
Patent number 5,781,241
PMODE
SD SC ADDR
I2C REGISTER & CONTROL
BLOCK
LINE
MEMORY
RSET
RSET
RR
ADC
Y
LINE RENDERING ENGINE
G
G COLOR
U
ADC
SPACE
-SCALING
CONVERTER
-DEFLICKERING
BB
V -SCAN CONVERSION
ADC
SYSTEM CLOCK
Y
U DIGITAL
NTSC/PAL
ENCODER
V & FILTER
DAC
DAC
DAC
VREF
PLL
TIMING & SYNC GENERATOR
OSC
VREF1 VREF2
XCLK
HV
Figure 1: Functional Block Diagram
XI XO
Y
CVBS
C
CLKOUT
201-0000-029 Rev 6.1, 8/2/99
1






CH7002D-V Datasheet, Funktion
CHRONTEL
CH7002D
Functional Description
The CH7002 is a fully integrated system solution for converting analog RGB and synchronization signals from a
standard VGA source into high-quality NTSC or PAL video signals. This solution involves both hardware and
software elements, which work together, to produce an optimum TV screen image based on the original computer
generated pixel data. All essential circuitry for this conversion are integrated on chip. On-chip circuitry includes:
memory, memory control, scaling, PLL, ADC, DAC, filters, and a NTSC/PAL encoder. All internal signal
processing, including NTSC/PAL encoding, is performed using digital techniques, to ensure that the high-quality
video signals are not affected by drift issues associated with analog components. No additional adjustment is
required during manufacturing.
CH7002 is ideal for stand-alone VGA to NTSC/PAL applications, where a minimum of discrete support
components (passive components, parallel resonance 14.31818 MHz crystal) are required for full operation. The
CH7002 is designed to provide an ideal solution for computer motherboards, add-on graphics cards, TV-sets, and
scan converter boards.
Architectural Overview
The CH7002 is a complete TV output subsystem, using both hardware and software elements, to produce an image
on TV, that is virtually identical to the image that would be displayed on a monitor. Creating a compatible TV
output from a VGA input is a relatively straightforward process. This process includes a standard conversion from
RGB to YUV color space, converting from a non-interlaced to an interlaced frame sequence, then encoding the
pixel stream into NTSC or PAL compliant format. However, creating an optimum computer-generated image on a
TV screen involves a highly sophisticated process of scaling, deflickering, and filtering. This results in a
compatible TV output that displays a sharp and stable image of the right size, with minimal artifacts from the
conversion process.
As a key part of the overall system solution, the CH7002 software establishes the correct framework for the VGA
input signal to enable this process. Once the display is set to a supported resolution (either 640x480 or 800x600),
the CH7002 software may be invoked to establish the appropriate TV output display. The software then programs
the various timing parameters of the VGA controller to create an output signal that will be compatible with the
chosen resolution, operating mode, and TV format. Adjustments performed in software include pixel clock rates,
total pixels per line, and total lines per frame. By performing these adjustments in software, the CH7002 can render
a superior TV image, without the added cost of a full frame buffer memory, normally used to implement features
such as scaling and full synchronization. Without this added system software, TV output solutions can only
guarantee compatible operation in VGA standard mode 12 (640x480x16 color, 60 Hz).
The CH7002 hardware accepts direct VGA outputs (analog RGB inputs), which are digitized on a pixel-by-pixel
basis by three 8-bit video A/D converters. The digitized RGB inputs are then color space converted into YUV in 4-
2-2 format (encoded into luminance (Y) and color-difference (U,V) signals) and stored in a line buffer memory.
The stored pixels are fed into a block where scan-rate conversion, underscan scaling, and 3-line vertical flicker
filtering are performed. The scan-rate converter transforms the VGA horizontal scan-rate to either NTSC or PAL
scan-rates; the vertical flicker filter eliminates flicker at the output, while the underscan scaling reduces the size of
the displayed image to fit onto a TV screen. The resulting YUV signals are filtered through digital filters to
minimize aliasing problems. The digital encoder receives the filtered signals and transforms the signals into
composite and S-Video outputs, which are converted by the three 8-bit DACs into analog outputs.
6 201-0000-029 Rev6.1, 8/2/99

6 Page









CH7002D-V pdf, datenblatt
CHRONTEL
CH7002D
NTSC and PAL Operation
Composite and S-Video outputs are supported in either NTSC or PAL format. The general parameters used to
characterize these outputs are listed in Table 4 and shown in Figure 8. (See Figures 9 through 16 for illustrations of
composite and S-Video output waveforms.)
Table 4. NTSC/PAL Composite Output Timing Parameters (in µS)
Symbol Description
Level (mV)
Duration (uS)
NTSC
PAL
NTSC
PAL
A Front Porch
B Horizontal Sync
C Breezeway
D Color Burst
E Back Porch
F Black
G Active Video
H Black
310
24
310
310
310
363
363-1030
363
310
24
310
310
310
310
310-977
310
1.49 - 1.52
4.69 - 4.72
0.60
2.48 - 2.50
1.60
0.92 - 3.64
45.40 - 50.84
0.92 - 3.64
1.50 - 1.78
4.43 - 4.73
0.57 - 0.60
2.33 - 2.52
1.50 - 1.60
0.00 - 4.24
45.20 - 53.00
0.00 - 4.24
Notes: For this table and all subsequent figures: RSET = 324 ohms; V(RSET) = 1.235 V; 75 ohms doubly terminated
load (BLR=61 for NTSC, and BLR=52 for PAL), 100% amplitude, 100% saturation bars are shown (100%=0.66071V).
1 Durations vary slightly in different modes due to the different clock frequencies used.
2 Active video times vary greatly due to different scaling ratios used in different modes.
3 Black times (F and H) vary with position controls.
A B C D EF
G
H
Figure 8: NTSC / PAL Composite Output
12 201-0000-029 Rev6.1, 8/2/99

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