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CH7001C Schematic ( PDF Datasheet ) - ETC

Teilenummer CH7001C
Beschreibung VGA to NTSC/PAL Encoder
Hersteller ETC
Logo ETC Logo 




Gesamt 18 Seiten
CH7001C Datasheet, Funktion
CHRONTEL
CH7001C
VGA to NTSC/PAL Encoder
Features
• Enhanced bandwidth and signal-to-noise ratio for
higher video performance
• Integrated triple video rate 8-bit analog to digital
converters for input RGB
• 3-line digital vertical filtering with pin-
programmable characteristics for optimum anti-
flicker and resolution
• On-chip phase-locked loop generates sampling
clock from VGA horizontal sync
• Enhanced power management for selective circuit
power-down
• Simultaneous composite/S-video output
• Horizontal and vertical position control
• Pin-programmable underscan/overscan mode
• On-chip reference generation and loop filter
• CMOS technology in 44-pin PLCC
• 5V supply
Description
Chrontel’s CH7001C VGA to NTSC/PAL encoder is a
stand-alone integrated circuit that converts analog VGA
inputs directly into 525-line (M) NTSC or 625-line
(B, D, G, H, I) PAL composite video and S-video
outputs.
This circuit integrates a digital NTSC/PAL encoder
with 8-bit ADC and DAC interfaces, a 3-line vertical
filter and low-jitter phase-locked loop to create
outstanding quality video with 24-bits-per-pixel proces-
sing throughout the entire signal path.
A high level of integration and performance makes the
CH7001C ideal for a variety of stand-alone and system-
level integration solutions, including notebook
computers and PC add-on graphics cards.
HORIZONTAL, VERTICAL
POSITION CONTROL
STROBE CLKOUT CLKEN* NTSC/PAL* PD[1:0] VDD DVDD AVDD RSET VREF1 VREF2
UNDERSCAN
MS[1:0]
R
G
B
H
V
BLANKING
H,V SYNC
GENERATOR
ADC
ADC
ADC
VERTICAL
FILTER
SCAN-RATE
CONVERTER
COLOR
SPACE
CONVERTER
PLL
SYSTEM CLOCKS
Y
FILTER
U
FILTER
RSET
VREF
M
U DAC
X
Σ DAC
M
UX
X
Σ
DAC
V
FILTER
M
U
X
X
BLANKING COLOR-BURST
CONTROL
SIN + COSINE
GENERATOR
OSC
Figure 1: Functional Block Diagram
Y
CVBS
C
201-0000-028 Rev 3.0, 6/2/99
1






CH7001C Datasheet, Funktion
CHRONTEL
CH7001C
Ferrite Bead
+5V
Ferrite Bead
Ferrite Bead
0.1uF 10uF +
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
VGA
Card
7404 7404
3
AVDD
35
H
34
V
4
R
2
G
44
B
38
AVDD
43
AVDD
18
VDD
25
VDD
9
DVDD
13
DVDD
32
DVDD
VREF1
41
39
VREF2
8
CLKOUT
0.1uF
0.1uF
To MONITOR or
TERMINATION
RESISTORS
Switch
Switch
(1)
2.2uF-4.7uF (2)
26 UP
27 DOWN
28 LEFT
29 RIGHT
12, 11
MS [1:0]
33
UNDERSCAN
30
NTSC/PAL*
7
CLKEN*
37,17
PD [0:1]
6
STROBE
36 TEST*
14.31818
MHz
16
XO/FIN
15 XI
AGND
1 5 40 42
CH7001C
(PLCC pinout)
GND
20 24
21 Ferrite Bead
Y
75 Ohms
23 Ferrite Bead
C
75 Ohms
Ferrite Bead
22
CVBS
75 Ohms
19
RSET
DGND
10 14 31
330 Ohms
Figure 4: CH7001C Typical Connection Diagram
Note: 1 If the CLKOUT signal is not used, either connect CLKEN* to VDD, or leave it unconnected.
Note: 2 An external pull-up resistor should not be connected to the TEST* pin.
6 201-0000-028 Rev 3.0, 6/2/99

6 Page









CH7001C pdf, datenblatt
CHRONTEL
CH7001C
General Description (continued)
Table 2 • NTSC/PAL Composite Output Timing Parameters (in µS)
Symbol Description
NTSC
OVERSCAN
UNDERSCAN
PAL
OVERSCAN
UNDERSCAN
A Front Porch
1.35
1.20
1.35
1.20
B Horizontal Sync
4.69
4.70
4.69
4.70
C Breezeway
0.64
0.57
0.56
0.49
D Color Burst
2.66
2.37
2.39
2.12
E Back Porch
1.47
1.31
1.83
1.63
F Black
2.38
5.10
2.37
5.11
G Active Video
50.51
45.19
50.51
45.19
H Black
0.00
3.12
0.00
3.12
ANALOG
FIELD 1
START
OF
VSYNC
520 521 522 523 524 525 1 2 3 4 5 6 7 8 9
ANALOG
FIELD 2
258 259 260 261 262 263 264 265 266 267 268 269 270 271 272
LINE RATE = HALF THE VGA LINE RATE IN MODES 11 & 12 (640 x 480)
FIELD RATE = VGA VERTICAL REFRESH RATE IN MODES 11 & 12 (640 x 480)
Figure 9: Interlaced NTSC Video Timing
12 201-0000-028 Rev 3.0, 6/2/99

12 Page





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