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74LV138BQ Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer 74LV138BQ
Beschreibung 3-to-8 line decoder/demultiplexer
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 16 Seiten
74LV138BQ Datasheet, Funktion
74LV138
3-to-8 line decoder/demultiplexer; inverting
Rev. 4 — 4 March 2016
Product data sheet
1. General description
The 74LV138 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC138 and 74HCT138.
The 74LV138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted
address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive
active LOW outputs (Y0 to Y7).
There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3).
Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the device to a 1-of-32
(5 lines to 32 lines) decoder with just four 74LV138 devices and one inverter. The
74LV138 can be used as an eight output demultiplexer by using one of the active LOW
enable inputs as the data input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their appropriate active HIGH or LOW state.
2. Features and benefits
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 C
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb = 25 C
Demultiplexing capability
Multiple input enable for easy expansion
Ideal for memory chip select decoding
Active LOW mutually exclusive outputs
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C






74LV138BQ Datasheet, Funktion
NXP Semiconductors
74LV138
3-to-8 line decoder/demultiplexer; inverting
Table 6. Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VOL
II
ICC
ICC
CI
LOW-level output voltage
input leakage current
supply current
additional supply current
input capacitance
VI = VIH or VIL
IO = 100 A; VCC = 1.2 V
IO = 100 A; VCC = 2.0 V
IO = 100 A; VCC = 2.7 V
IO = 100 A; VCC = 3.0 V
IO = 100 A; VCC = 4.5 V
IO = 6 mA; VCC = 3.0 V
IO = 12 mA; VCC = 4.5 V
VI = VCC or GND;
VCC = 5.5 V
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
per input; VI = VCC 0.6 V;
VCC = 2.7 V to 3.6 V
[1] Typical values are measured at Tamb = 25 C.
10. Dynamic characteristics
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max Min Max
- 0 - - -V
- 0 0.2 - 0.2 V
- 0 0.2 - 0.2 V
- 0 0.2 - 0.2 V
- 0 0.2 - 0.2 V
- 0.25 0.40 - 0.50 V
- 0.35 0.55 - 0.65 V
- - 1.0 - 1.0 A
- - 20.0 - 160 A
- - 500 - 850 A
- 3.5 - - - pF
Table 7. Dynamic characteristics
GND = 0 V; For test circuit see Figure 8.
Symbol Parameter
Conditions
40 C to +85 C
Min Typ[1] Max
tpd propagation delay An to Yn; see Figure 6
[2]
VCC = 1.2 V
- 75 -
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
[3]
[3]
-
-
-
-
26 44
19 31
12 -
15 26
VCC = 4.5 V to 5.5 V
- - 17
E3, En to Yn; see Figure 6 and
Figure 7
VCC = 1.2 V
- 75 -
VCC = 2.0 V
- 26 43
VCC = 2.7 V
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
[3]
[3]
-
-
-
19 30
14 -
15 25
VCC = 4.5 V to 5.5 V
- - 19
40 C to +125 C Unit
Min Max
- - ns
- 55 ns
- 39 ns
- - ns
- 32 ns
- 22 ns
- - ns
- 53 ns
- 38 ns
- - ns
- 31 ns
- 24 ns
74LV138
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 4 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
6 of 16

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74LV138BQ pdf, datenblatt
NXP Semiconductors
74LV138
3-to-8 line decoder/demultiplexer; inverting
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74LV138
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 4 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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