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IS46TR16640BL Schematic ( PDF Datasheet ) - ISSI

Teilenummer IS46TR16640BL
Beschreibung 1Gb DDR3 SDRAM
Hersteller ISSI
Logo ISSI Logo 




Gesamt 30 Seiten
IS46TR16640BL Datasheet, Funktion
IS43/46TR16640B, IS43/46TR16640BL
IS43/46TR81280B, IS43/46TR81280BL
128MX8, 64MX16 1Gb DDR3 SDRAM
FEATURES
Standard Voltage: VDD and VDDQ = 1.5V ± 0.075V
Low Voltage (L): VDD and VDDQ = 1.35V + 0.1V, -0.067V
- Backward compatible to 1.5V
High speed data transfer rates with system
frequency up to 1066 MHz
8 internal banks for concurrent operation
8n-bit pre-fetch architecture
Programmable CAS Latency
Programmable Additive Latency: 0, CL-1,CL-2
Programmable CAS WRITE latency (CWL) based
on tCK
Programmable Burst Length: 4 and 8
Programmable Burst Sequence: Sequential or
Interleave
BL switch on the fly
Auto Self Refresh(ASR)
Self Refresh Temperature(SRT)
OPTIONS
Configuration:
128Mx8
64Mx16
Package:
96-ball FBGA (9mm x 13mm) for x16
78-ball FBGA (8mm x 10.5mm) for x8
NOVEMBER 2014
Refresh Interval:
7.8 us (8192 cycles/64 ms) Tc= -40°C to 85°C
3.9 us (8192 cycles/32 ms) Tc= 85°C to 105°C
Partial Array Self Refresh
Asynchronous RESET pin
TDQS (Termination Data Strobe) supported (x8
only)
OCD (Off-Chip Driver Impedance Adjustment)
Dynamic ODT (On-Die Termination)
Driver strength : RZQ/7, RZQ/6 (RZQ = 240 )
Write Leveling
Operating temperature:
Commercial (TC = 0°C to +95°C)
Industrial (TC = -40°C to +95°C)
Automotive, A1 (TC = -40°C to +95°C)
Automotive, A2 (TC = -40°C to +105°C)
ADDRESS TABLE
Parameter
Row Addressing
Column Addressing
Bank Addressing
Page size
Auto Precharge Addressing
BL switch on the fly
128Mx8
A0-A13
A0-A9
BA0-2
1KB
A10/AP
A12/BC#
64Mx16
A0-A12
A0-A9
BA0-2
2KB
A10/AP
A12/BC#
SPEED BIN
Speed Option
15G
125J
107M
093N
JEDEC Speed Grade
DDR3-1333G DDR3-1600J DDR3-1866M DDR3-2133N
CL-nRCD-nRP
8-8-8
10-10-10
13-13-13
14-14-14
tRCD,tRP(min)
12.0
12.5
13.91
13.09
Note: Faster speed options may be backward compatible to slower speed options. Refer to timing tables (8.3)
Units
tCK
ns
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised
to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product
can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use
in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. www.issi.com
Rev. C1
11/12/2014
1






IS46TR16640BL Datasheet, Funktion
IS43/46TR16640B, IS43/46TR16640BL
IS43/46TR81280B, IS43/46TR81280BL
2.2 RESET and Initialization Procedure
2.2.1 Power-up Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power (RESET# is recommended to be maintained below 0.2 x VDD; all other inputs may be undefined).
RESET# needs to be maintained for minimum 200 us with stable power. CKE is pulled Low” anytime before
RESET# being de-asserted (min. time 10 ns). The power voltage ramp time between 300mV to VDD(min) must be
no greater than 200 ms; and during the ramp, VDD > VDDQ and (VDD - VDDQ) < 0.3 volts.
OR
VDD and VDDQ are driven from a single power converter output, AND
The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD
on one side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to
0.95 V max once power ramp is finished, AND
Vref tracks VDDQ/2.
Apply VDD without any slope reversal before or at the same time as VDDQ.
Apply VDDQ without any slope reversal before or at the same time as VTT & Vref.
The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD
on one side and must be larger than or equal to VSSQ and VSS on the other side.
2. After RESET# is de-asserted, wait for another 500 us until CKE becomes active. During this time, the DRAM will
start internal state initialization; this will be done independently of external clocks.
3. Clocks (CK, CK#) need to be started and stabilized for at least 10 ns or 5 tCK (which is larger) before CKE goes
active. Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be met. Also, a NOP or
Deselect command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE is
registered “High” after Reset, CKE needs to be continuously registered “High” until the initialization sequence is
finished, including expiration of tDLLK and tZQinit.
4. The DDR3 SDRAM keeps its on-die termination in high-impedance state as long as RESET# is asserted. Further,
the SDRAM keeps its on-die termination in high impedance state after RESET# deassertion until CKE is registered
HIGH. The ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is
registered HIGH, the ODT input signal may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled
in MR1, the ODT input signal must be statically held LOW. In all cases, the ODT input signal remains static until the
power up initialization sequence is finished, including the expiration of tDLLK and tZQinit.
5. After CKE is being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS
command to load mode register. (tXPR=max (tXS ; 5 x tCK)
6. Issue MRS Command to load MR2 with all application settings. (To issue MRS command for MR2, provide “Low” to
BA0 and BA2, “High” to BA1.)
7. Issue MRS Command to load MR3 with all application settings. (To issue MRS command for MR3, provide “Low” to
BA2, “High” to BA0 and BA1.)
8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue "DLL Enable" command,
provide "Low" to A0, "High" to BA0 and "Low" to BA1 BA2).
Integrated Silicon Solution, Inc. www.issi.com
Rev. C1
11/12/2014
6

6 Page









IS46TR16640BL pdf, datenblatt
IS43/46TR16640B, IS43/46TR16640BL
IS43/46TR81280B, IS43/46TR81280BL
2.3.2.5 Write Recovery
The programmed WR value MR0 (bits A9, A10, and A11) is used for the auto precharge feature along with tRP to
determine tDAL. WR (write recovery for auto-precharge) min in clock cycles is calculated by dividing tWR (in ns) by tCK
(in ns) and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR must be programmed to
be equal to or larger than tWR(min).
2.3.2.6 Precharge PD DLL
MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12 = 0), or ‘slow-exit’,
the DLL is frozen after entering precharge power-down (for potential power savings) and upon exit requires tXPDLL to be
met prior to the next valid command. When MR0 (A12 = 1), or ‘fast-exit’, the DLL is maintained after entering precharge
power-down and upon exiting power-down requires tXP to be met prior to the next valid command.
2.3.3 Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, Rtt_Nom impedance,
additive latency, Write leveling enable, TDQS enable and Qoff. The Mode Register 1 is written by asserting low on CS#,
RAS#, CAS#, WE#, high on BA0 and low on BA1 and BA2, while controlling the states of address pins according to
Figure 2.3.3.
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
001
0* 1
Qoff TDQS 0*1 Rtt 0*1 Level Rtt D.I.C AL
Rtt D.I.C DLL Mode Register 1
A11 TDQS enable
0 Disabled
1 Enabled
A7 Write leveling enable
0 Disabled
1 Enabled
A4 A3
00
01
10
11
Additive Latency
0 (AL disabled)
CL-1
CL-2
Reserved
A12 Qoff *2
0 Output buffer enabled
1 Output buffer disabled *2
*2: Outputs disabled - DQs, DQSs, DQS#s.
BA1 BA0
00
01
10
11
MR Select
MR0
MR1
MR2
MR3
A9 A6 A2
Rtt_Nom *3
A0
000
ODT disabled
0
001
RZQ/4
1
010
RZQ/2
011
RZQ/6
100
RZQ/12 *4
101
RZQ/8*4
110
Reserved
111
Reserved
Note: RZQ = 240
*3:In Write leveling Mode (MR1[bit7] = 1) with
MR1[bit12]=1, all RTT_Nom settings are allowed; in
Write Leveling Mode (MR1[bit7] = 1) with
MR1[bit12]=0, only RTT_Nom settings of RZQ/2,
RZQ/4 and RZQ/6 are allowed.
*4:If RTT_Nom is used during Writes, only the
values RZQ/2, RZQ/4 and RZQ/6 are allowed.
DLL Enable
Enable
Disable
A5 A1
00
01
10
11
Output Driver Impedance Control
RZQ/6
RZQ/7
RZQ/TBD
RZQ/TBD
* 1 : A8, A10, and A13 must be programmed to 0 during MRS.
* TDQS must be disabled for x16 option.
Figure 2.3.3 MR1 Definition
Integrated Silicon Solution, Inc. www.issi.com
Rev. C1
11/12/2014
12

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