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IS43DR16640C Schematic ( PDF Datasheet ) - ISSI

Teilenummer IS43DR16640C
Beschreibung DDR2 DRAM
Hersteller ISSI
Logo ISSI Logo 




Gesamt 30 Seiten
IS43DR16640C Datasheet, Funktion
IS43/46DR81280C
IS43/46DR16640C
128Mx8, 64Mx16 DDR2 DRAM
FEATURES
Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Double data rate interface: two data transfers
per clock cycle
Differential data strobe (DQS, DQS)
4-bit prefetch architecture
On chip DLL to align DQ and DQS transitions
with CK
8 internal banks for concurrent operation
Programmable CAS latency (CL) 3, 4, 5, 6 and 7
supported
Posted CAS and programmable additive latency
(AL) 0, 1, 2, 3, 4, 5 and 6 supported
WRITE latency = READ latency - 1 tCK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength, full and
reduced strength options
On-die termination (ODT)
ADVANCED INFORMATION
DESCRIPTION
MAY 2013
ISSI's 1Gb DDR2 SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The
double-data rate architecture is essentially a 4n-prefetch
architecture, with an interface designed to transfer two
data words per clock cycle at the I/O balls.
ADDRESS TABLE
Parameter
Configuration
Refresh Count
128M x 8
16M x 8 x 8
banks
8K/64ms
64M x 16
8M x 16 x 8
banks
8K/64ms
Row Addressing 16K (A0-A13) 8K (A0-A12)
Column
Addressing
1K (A0-A9)
Bank Addressing BA0 - BA2
1K (A0-A9)
BA0 - BA2
Precharge
Addressing
A10
A10
OPTIONS
Configuration(s):
128Mx8 (16Mx8x8 banks): IS43/46DR81280C
64Mx16 (8Mx16x8 banks): IS43/46DR16640C
Package:
x8: 60-ball BGA (8mm x 10.5mm)
x16: 84-ball WBGA (8mm x 12.5mm)
Timing – Cycle time
2.5ns @CL=5 DDR2-800D
2.5ns @CL=6 DDR2-800E
3.0ns @CL=5 DDR2-667D
3.75ns @CL=4 DDR2-533C
5ns @CL=3 DDR2-400B
Temperature Range:
Commercial (0°C Tc 85°C)
Industrial (-40°C Tc 95°C; -40°C Ta 85°C)
Automotive, A1 (-40°C Tc 95°C; -40°C Ta 85°C)
Automotive, A2 (-40°C Tc; Ta 105°C)
Tc = Case Temp, Ta = Ambient Temp
KEY TIMING PARAMETERS
Speed Grade -25D -3D
tRCD
12.5 15
tRP 12.5 15
tRC 55 55
tRAS
40 40
tCK @CL=3
55
tCK @CL=4
3.75 3.75
tCK @CL=5
2.5 3
tCK @CL=6
2.5 —
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest
version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. 00A
6/4/2013






IS43DR16640C Datasheet, Funktion
IS43/46DR81280C, IS43/46DR16640C
PIN CONFIGURATION
PACKAGE CODE: B 84 BALL FBGA (Top View) (8.00 mm x 12.50 mm Body, 0.8 mm Ball Pitch)
123456789
A
VDD NC VSS
B
C DQ14 VSSQ UDM
VDDQ DQ9 VDDQ
D
DQ12 VSSQ DQ11
E
F VDD NC VSS
DQ6 VSSQ LDM
G
H VDDQ DQ1 VDDQ
J DQ4 VSSQ DQ3
VDDL VREF VSS
K
CKE WE
L
M BA2 BA0 BA1
N VSS A10/AP A1
P A3 A5
R VDD A7 A9
A12 NC
Pin name
A0 to A12
BA0 to BA2
DQ0 to DQ15
LDQS, UDQS
/LDQS, /UDQS
/CS
/RAS, /CAS, /WE
CKE
CK, /CK
LDM to UDM
Function
Address inputs
Bank select
Data input/output
Differential data strobe
Chip select
Command input
Clock enable
Differential clock input
Write data mask
6
VSSQ UDQS VDDQ
UDQS VSSQ DQ15
VDDQ DQ8 VDDQ
DQ10 VSSQ DQ13
VSSQ LDQS VDDQ
LDQS VSSQ DQ7
VDDQ DQ0 VDDQ
DQ2 VSSQ DQ5
VSSDL CK VDD
RAS CK ODT
CAS CS
A2 A0 VDD
A6 A4
A11 A8 VSS
NC NC
Not populated
Pin name
ODT
VDD
VSS
VDDQ
Function
ODT control
Supply voltage for internal circuit
Ground for internal circuit
Supply voltage for DQ circuit
VSSQ
VREF
VDDL
VSSDL
NC
Ground for DQ circuit
Input reference voltage
Supply voltage for DLL circuit
Ground for DLL circuit
No connection
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
6/4/2013

6 Page









IS43DR16640C pdf, datenblatt
IS43/46DR81280C, IS43/46DR16640C
Output Buffer Characteristics
Output AC Test Conditions
Symbol
VOTR
Parameter
Output Timing Measurement Reference Level
SSTL_18
0.5 x VDDQ
Units Notes
V1
Output DC Current Drive
Symbol
IOH(dc)
IOL(dc)
Parameter
Output Minimum Source DC Current
Output Minimum Sink DC Current
SSTL_18
- 13.4
13.4
Units
mA
mA
Notes
1, 3, 4
2, 3, 4
Notes:
1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 Ω for values of VOUT between VDDQ and VDDQ - 280 mV.
2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 Ω for values of VOUT between 0 V and 280 mV.
3. The dc value of VREF applied to the receiving device is set to VTT
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to
ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are
derived by shifting the desired driver operating point (see Section 3.3 of JESD8-15A) along a 21 Ω load line to define a convenient driver cur-
rent for measurement.
OCD Default Characteristics
Description
Parameter Min Nom Max Unit Notes
Output impedance
See full strength default
driver characteristics
Ω1
Output impedance step size
for OCD calibration
0 1.5 Ω 6
Pull-up and pull-down
mismatch
0 4 Ω 1,2,3
Output slew rate
Sout
1.5
5 V/ns 1,4,5,7,8,9
Notes:
1. Absolute Specifications (TOPER; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V). DRAM I/O specifications for timing, voltage, and slew rate are no
longer applicable if OCD is changed from default settings.
2. Impedance measurement condition for output source dc current: VDDQ = 1.7 V; VOUT = 1420 mV; (VOUTVDDQ)/IOH must be less than 23.4
Ω for values of VOUT between VDDQ and VDDQ - 280 mV. Impedance measurement condition for output sink dc current: VDDQ = 1.7 V;
VOUT = 280 mV; VOUT/IOL must be less than 23.4 Ω for values of VOUT between 0 V and 280 mV.
3. Mismatch is absolute value between pull-up and pull-down, both are measured at same temperature and voltage.
4. Slew rate measured from VIL(ac) to VIH(ac).
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is
guaranteed by design and characterization.
6. This represents the step size when the OCD is near 18 Ω at nominal conditions across all process corners/variations and represents only the
DRAM uncertainty. A 0 Ω value (no calibration) can only be achieved if the OCD impedance is 18 Ω +/-0.75 Ω under nominal conditions.
7. DRAM output slew rate specification applies to 400 MT/s, 533 MT/s & 667 MT/s speed bins.
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQ’s is included in tDQSQ and tQHS specification.
9. DDR2 SDRAM output slew rate test load is defined in General Note 3 of the AC Timing specification Table.
12 Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
6/4/2013

12 Page





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