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IS43DR32801B Schematic ( PDF Datasheet ) - ISSI

Teilenummer IS43DR32801B
Beschreibung 8Mx32 256Mb DDR2 DRAM
Hersteller ISSI
Logo ISSI Logo 




Gesamt 30 Seiten
IS43DR32801B Datasheet, Funktion
IS43/46DR32801B
8Mx32
256Mb DDR2 DRAM
FEATURES
• Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Double data rate interface: two data transfers
per clock cycle
• Differential data strobe (DQS, DQS)
• 4-bit prefetch architecture
• On chip DLL to align DQ and DQS transitions
with CK
• 4 internal banks for concurrent operation
• Programmable CAS latency (CL) 3, 4, 5, and 6
supported
• Posted CAS and programmable additive latency
(AL) 0, 1, 2, 3, 4, and 5 supported
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength, full and
reduced strength options
• On-die termination (ODT)
OPTIONS
• Configuration:
8M x 32 (IS43/46DR32801B - 8K refresh)
• Package: x32: 126-ball WBGA
• Timing – Cycle time
2.5ns @CL=6, DDR2-800E
3.0ns @CL=5, DDR2-667D
3.75ns @CL=4, DDR2-533C
5.0ns @CL=3, DDR2-400B
• Temperature Range:
Commercial (0°C Tc 85°C; 0°C Ta 70°C)
Industrial (–40°C Tc 95°C; –40°C Ta 85°C)
Automotive, A1 (–40°C Tc 95°C; –40°C Ta 85°C)
Automotive, A2 (–40°C Tc 105°C; –40°C Ta 105°C)
Tc = Case Temp, Ta = Ambient Temp
ADVANCED INFORMATION
JUNE 2012
DESCRIPTION
ISSI's 256Mb DDR2 SDRAM uses a double-data-rate
architecture to achieve high-speed operation. The
double-data rate architecture is essentially a 4n-prefetch
architecture, with an interface designed to transfer two
data words per clock cycle at the I/O balls.
The 256Mb DDR2 SDRAM is provided in a wide bus
x32 format, designed to offer a smaller footprint and
support compact designs.
ADDRESS TABLE
Parameter
Configuration
Refresh Count
Row Addressing
Column
Addressing
Bank Addressing
Precharge
Addressing
8M x 32
4M x 32 x 4 banks
8K/64ms
A0-A12
A0-A7
BA0, BA1
A10/AP
KEY TIMING PARAMETERS
Speed Grade -25E -3D -37C
tRCD
15 15 15
tRP 15 15 15
tRC 60 60 60
tRAS
45 45 45
tCK @CL=3
555
tCK @CL=4
3.75 3.75 3.75
tCK @CL=5
3 3 3.75
tCK @CL=6
2.5 3 3.75
-5B
15
15
55
40
5
5
5
5
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  00B
06/07/2012
1






IS43DR32801B Datasheet, Funktion
IS43/46DR32801B
electrical specifications
Absolute Maximum DC Ratings
Symbol
Vdd
Vddq
Vddl
Vin, Vout
Tstg
Parameter
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on VDDL pin relative to Vss
Voltage on any pin relative to Vss
Storage Temperature
Rating
- 1.0 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +150
Units
V
V
V
V
°C
Notes
1,3
1,3
1,3
1,4
1, 2
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to
JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ. When VDD and VDDQ and
VDDL are less than 500 mV, Vref may be equal to or less than 300 mV.
4. Voltage on any input or I/O may not exceed voltage on VDDQ.
AC & DC Recommended Operating Conditions
Recommended DC Operating Conditions (SSTL-1.8)
Symbol Parameter
Rating
Units Notes
Min.
Typ.
Max.
VDD
Supply Voltage
1.7 1.8 1.9 V 1
VDDL Supply Voltage for DLL
1.7
1.8
1.9 V 5
VDDQ Supply Voltage for Output
1.7
1.8
1.9 V 1, 5
VREF
Input Reference Voltage
0.49 x VDDQ 0.50 x VDDQ 0.51 x VDDQ mV 2. 3
VTT Termination Voltage
VREF - 0.04
VREF
VREF + 0.04 V 4
Notes:
1. There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However under all conditions VDDQ must be less than
or equal to VDD.
2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be
about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
3. Peak to peak ac noise on VREF may not exceed +/-2 % VREF(dc).
4. VTT of transmitting device must track VREF of receiving device.
5. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together
6 Integrated Silicon Solution, Inc. — www.issi.com
Rev.  00B
06/07/2012

6 Page









IS43DR32801B pdf, datenblatt
IS43/46DR32801B
IDD Specifications & Test Conditions
Symbol Conditions
IDD0
IDD1
Operating one bank active-precharge current;
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);
CKE is HIGH, CS is HIGH between valid commands;
50% of Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD);
CKE is HIGH, CS is HIGH between valid commands;
50% of Address bus inputs are SWITCHING; Data pattern is same as IDD4W
-25E -3D -37C -5B Units
DDR2- DDR2- DDR2- DDR2-
800E 667D 533C 400B
150 140 130 120 mA
175 165 165 150 mA
IDD2P
Precharge power-down current; All banks idle;
tCK = tCK(IDD); CKE is LOW;
Other control and address bus inputs are STABLE;
8 8 8 8 mA
Data bus inputs are FLOATING
IDD2Q Precharge quiet standby current; All banks idle;
tCK = tCK(IDD);
CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; 75 65 55 45 mA
Data bus inputs are FLOATING
Precharge standby current; All banks idle;
tCK = tCK(IDD);
IDD2N CKE is HIGH, CS is HIGH; Other control and 50% of address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
90 80 70 60 mA
Active power-down current; All banks open;
IDD3P tCK = tCK(IDD); CKE is LOW;
Other control and address bus inputs are STABLE;
25 20 20 15 mA
Data bus inputs are FLOATING
IDD3N Active standby current; All banks open;
tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Other control and 50% of address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
80 70 60 50 mA
IDD4W Operating burst write current; All banks open, Continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =
tRP(IDD);
CKE is HIGH, CS is HIGH between valid commands;
390 320 280 210 mA
50% of Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
12 Integrated Silicon Solution, Inc. — www.issi.com
Rev.  00B
06/07/2012

12 Page





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