Datenblatt-pdf.com


IS42RM16160E Schematic ( PDF Datasheet ) - ISSI

Teilenummer IS42RM16160E
Beschreibung 4M x 16Bits x 4Banks Mobile Synchronous DRAM
Hersteller ISSI
Logo ISSI Logo 




Gesamt 30 Seiten
IS42RM16160E Datasheet, Funktion
IS42/45SM/RM/VM16160E
4M x 16Bits x 4Banks Mobile Synchronous DRAM
Description
These IS42/45SM/RM/VM16160E are mobile 268,435,456 bits CMOS Synchronous DRAM organized as 4 banks of 4,194,304 words x 16
bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input
and output voltage levels are compatible with LVCMOS.
Features
JEDEC standard 3.3V, 2.5V, 1.8V power supply.
Auto refresh and self refresh.
All pins are compatible with LVCMOS interface.
8K refresh cycle / 64ms.
Programmable Burst Length and Burst Type.
- 1, 2, 4, 8 or Full Page for Sequential Burst.
- 4 or 8 for Interleave Burst.
Programmable CAS Latency : 2,3 clocks.
All inputs and outputs referenced to the positive edge of the
system clock.
Data mask function by DQM.
Internal 4 banks operation.
Burst Read Single Write operation.
Special Function Support.
- PASR(Partial Array Self Refresh)
- Auto TCSR(Temperature Compensated Self Refresh)
- Programmable Driver Strength Control
Full Strength or 3/4, 1/2, 1/4, 1/8 of Full Strength
- Deep Power Down Mode
Automatic precharge, includes CONCURRENT Auto Precharge
Mode and controlled Precharge.
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Rev. 0C | May 2013
www.issi.com - [email protected]
1






IS42RM16160E Datasheet, Funktion
IS42/45SM/RM/VM16160E
Figure4: Mode Register Definition
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
14 13
12 11
10
9
8
7
0 0 0 0 0 WB 0 0
6543
CAS Latency
BT
210
Burst Length
Mode Register (Mx)
M9 Write Burst Mode
0 Burst Read and Burst Write
1 Burst Read and Single Write
M6 M5 M4 CAS Latency
000
Reserved
001
Reserved
010
2
011
3
100
Reserved
101
Reserved
110
Reserved
111
Reserved
M3 Burst Type
0 Sequential
1 Interleave
M2 M1 M0
000
001
010
011
100
101
110
111
Note: M14 (BA1) and M13 (BA0) must be set to “0” to select Mode Register (vs. the Extended Mode Register)
Burst Length
M3 = 0
M3 = 1
11
22
44
88
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is
selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column
address, as shown in Table 3.
Table 3: Burst Definition
Burst
Length
Starting Column
Address
A2 A1 A0
Order of Access Within a Burst
Sequential
Interleaved
2
0 0-1
1 1-0
0-1
1-0
00
0-1-2-3
0-1-2-3
01
1-2-3-0
1-0-3-2
4
10
2-3-0-1
2-3-0-1
11
3-0-1-2
3-2-1-0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
8
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Full
Page
n=A0-8
(Location 0-511)
Cn, Cn+1. Cn+2,
Cn+3, Cn+4…
…Cn-1, Cn...
Not Supported
Note :
1. For full-page accesses: y = 512
2. For a burst length of two, A1-A8 select the block-
of-two burst; A0 selects the starting column within the
block.
3. For a burst length of four, A2-A8 select the block-
of-four burst; A0-A1 select the starting column within
the block.
4. For a burst length of eight, A3-A8 select the
block-of-eight burst; A0-A2 select the starting column
within the block.
5. For a full-page burst, the full row is selected and A0-A8
select the starting column.
6. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
7. For a burst length of one, A0-A8 select the unique
column to be accessed, and mode register bit M3 is
ignored.
Rev. 0C | May 2013
www.issi.com - [email protected]
6

6 Page









IS42RM16160E pdf, datenblatt
IS42/45SM/RM/VM16160E
Table5: Function Truth Table
Current
Command
State
/CS /RAS /CAS /WE
BA
A0-A12
LLLL
OP CODE
Description
Mode Register Set
L L L HX
X Auto or Self Refresh
L L H L BA
X Precharge
L
L
H H BA
Row Add.
Bank Activate
Idle
L H L L BA Col Add./ A10 Write/WriteAP
L H L H BA Col Add./ A10 Read/ReadAP
L HHHX
X No Operation
HX XXX
X Device Deselect
LLLL
OP CODE
Mode Register Set
L L L HX
X Auto or Self Refresh
L L H L BA
X Precharge
L
L
H H BA
Row Add.
Bank Activate
Row
Active
L
H
L
L BA Col Add./A10 Write/Write AP
L H L H BA Col Add./A10 Read/Read AP
L HHHX
X
HX XXX
X
LLLL
OP CODE
L L L HX
X
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
L L H L BA
X Precharge
L
L
H H BA
Row Add.
Bank Activate
Read
L H L L BA Col Add./A10 Write/WriteAP
L H L H BA Col Add./A10 Read/Read AP
L HHHX
HX XXX
X No Operation
X Device Deselect
Action
Note
Set the Mode Register
Start Auto or Self
Refresh
No Operation
Activate the Specified
Bank and Row
ILLEGAL
ILLEGAL
No Operation
No Operation or Power
Down
ILLEGAL
ILLEGAL
Precharge
ILLEGAL
Start Write : Optional
AP(A10=H)
Start Read : Optional
AP(A10=H)
No Operation
No Operation
ILLEGAL
ILLEGAL
Termination Burst :
Start the Precharge
ILLEGAL
Termination Burst :
Start Write(AP)
Terimination Burst :
Start Read(AP)
Continue the Burst
Continue the Burst
14
5
4
4
3
3
13,14
13
7
4
6
6
13,14
13
4
8,9
8
Rev. 0C | May 2013
www.issi.com - [email protected]
12

12 Page





SeitenGesamt 30 Seiten
PDF Download[ IS42RM16160E Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
IS42RM16160E4M x 16Bits x 4Banks Mobile Synchronous DRAMISSI
ISSI

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche