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IS25LQ010B Schematic ( PDF Datasheet ) - ISSI

Teilenummer IS25LQ010B
Beschreibung 3V QUAD SERIAL FLASH MEMORY
Hersteller ISSI
Logo ISSI Logo 




Gesamt 30 Seiten
IS25LQ010B Datasheet, Funktion
IS25LQ025B
IS25LQ512B
IS25LQ010B
IS25LQ020B
IS25LQ040B
256K/512K/1M/2M/4MBIT
3V QUAD SERIAL FLASH MEMORY WITH
MULTI-I/O SPI






IS25LQ010B Datasheet, Funktion
IS25LQ025/512/010/020/040B
2. PIN DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
Chip Enable: The Chip Enable (CE#) pin enables and disables the devices operation.
When CE# is high the device is deselected and output pins are in a high impedance
state. When deselected the devices non-critical internal circuitry power down to allow
minimal levels of power consumption while in a standby state.
CE#
INPUT
When CE# is pulled low the device will be selected and brought out of standby mode.
The device is considered active and instructions can be written to, data read, and
written to the device. After power-up, CE# must transition from high to low before a
new instruction will be accepted.
Keeping CE# in a high state deselects the device and switches it into its low power
state. Data will not be accepted when CE# is high.
SI (IO0),
SO (IO1)
INPUT/OUTPUT
Serial Data Input, Serial Output, and IOs (SI, SO, IO0, and IO1):
This device supports standard SPI, Dual SPI, and Quad SPI operation. Standard SPI
instructions use the unidirectional SI (Serial Input) pin to write instructions, addresses,
or data to the device on the rising edge of the Serial Clock (SCK). Standard SPI also
uses the unidirectional SO (Serial Output) to read data or status from the device on
the falling edge of the serial clock (SCK).
In Dual and Quad SPI mode, SI and SO become bidirectional IO pins to write
instructions, addresses or data to the device on the rising edge of the Serial Clock
(SCK) and read data or status from the device on the falling edge of SCK. Quad SPI
instructions use the WP# and HOLD# pins as IO2 and IO3 respectively.
WP# (IO2)
INPUT/OUTPUT
Write Protect/Serial Data IO (IO2): The WP# pin protects the Status Register from
being written in conjunction with the SRWD bit. When the SRWD is set to “1” and the
WP# is pulled low, the Status Register bits (SRWD, QE, BP3, BP2, BP1, BP0) are
write-protected and vice-versa for WP# high. When the SRWD is set to “0”, the Status
Register is not write-protected regardless of WP# state.
When the QE bit is set to “1”, the WP# pin (Write Protect) function is not available
since this pin is used for IO2.
HOLD# (IO3)
INPUT/OUTPUT
Hold/Serial Data IO (IO3): Pauses serial communication by the master device
without resetting the serial sequence. When the QE bit of Status Register is set to
“1”, HOLD# pin is not available since it becomes IO3.
The HOLD# pin allows the device to be paused while it is selected. The HOLD# pin is
active low. When HOLD# is in a low state, and CE# is low, the SO pin will be at high
impedance.
Device operation can resume when HOLD# pin is brought to a high state. When the
QE bit of Status Register is set for Quad I/O, the HOLD# pin function is not available
and becomes IO3 for Multi-I/O SPI mode.
SCK
Vcc
GND
NC
INPUT
POWER
GROUND
Unused
Serial Data Clock: Synchronized Clock for input and output timing operations.
Power: Device Core Power Supply
Ground: Connect to ground when referenced to Vcc
NC: Pins labeled “NC” stand for “No Connect” and should be left uncommitted.
Integrated Silicon Solution, Inc.- www.issi.com
Rev.A
12/12/2014
6

6 Page









IS25LQ010B pdf, datenblatt
IS25LQ025/512/010/020/040B
6. REGISTERS
The IS25LQ025/512/010/020/040B has two sets of Registers: Status, Function.
6.1. STATUS REGISTER
Status Register Format and Status Register Bit Definitions are described in Tables 6.1 & 6.2.
Table 6.1 Status Register Format
Bit 7
Bit 6
SRWD
QE
Default
00
Bit 5
BP3
0
Bit 4
BP2
0
Bit 3
BP1
0
Bit 2
BP0
0
Bit 1
WEL
0
Bit 0
WIP
0
Table 6.2 Status Register Bit Definition
Bit Name
Definition
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
WIP
WEL
BP0
BP1
BP2
BP3
QE
SRWD
Write In Progress Bit:
"0" indicates the device is ready(default)
"1" indicates a write cycle is in progress and the device is busy
Write Enable Latch:
"0" indicates the device is not write enabled (default)
"1" indicates the device is write enabled
Block Protection Bit: (See Tables 6.4 for details)
"0" indicates the specific blocks are not write-protected (default)
"1" indicates the specific blocks are write-protected
Quad Enable bit:
“0” indicates the Quad output function disable (default)
“1” indicates the Quad output function enable
Status Register Write Disable: (See Table 7.1 for details)
"0" indicates the Status Register is not write-protected (default)
"1" indicates the Status Register is write-protected
Read-
/Write
R
R
Type
Volatile
Volatile
R/W Non-Volatile
R/W Non-Volatile
R/W Non-Volatile
The BP0, BP1, BP2, BP3 and SRWD are non-volatile memory cells that can be written by a Write Status Register
(WRSR) instruction. The default value of the BP2, BP1, BP0, and SRWD bits were set to “0” at factory. The
Status Register can be read by the Read Status Register (RDSR).
The function of Status Register bits are described as follows:
WIP bit: The Write In Progress (WIP) bit is read-only, and can be used to detect the progress or completion of a
program or erase operation. When the WIP bit is “0”, the device is ready for write Status or Function Register,
program or erase operation. When the WIP bit is “1”, the device is busy.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal write enable latch. When the WEL
is “0”, the write enable latch is disabled and all write operations described in Table 6.3 are inhibited. When the
WEL bit is “1”, write operations are allowed. The WEL bit is set by a Write Enable (WREN) instruction. Each write
register, program and erase instruction must be preceded by a WREN instruction. The WEL bit can be reset by a
Write Disable (WRDI) instruction. It will automatically be reset after the completion of any write operation.
Integrated Silicon Solution, Inc.- www.issi.com
Rev.A
12/12/2014
12

12 Page





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