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CW24C128 Schematic ( PDF Datasheet ) - ChipsWinner

Teilenummer CW24C128
Beschreibung 128Kbit and 256Kbit Serial I2C Bus EEPROM
Hersteller ChipsWinner
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Gesamt 14 Seiten
CW24C128 Datasheet, Funktion
CW 24C 93C SOP/TSSOP 8205A
CW24C128/CW24C256
128Kbit and 256Kbit Serial I²C Bus EEPROM
DESCRIPTION
PIN CONFIGURATION
The CW24C128/256 is Electrically Erasable PROM. The device
is organized as one block of 16384/32768 x 8-bit memory with
2-wire serial interface. Low-voltage design permits operation
A0 1
A1 2
8 VCC
7 WP
down to 1.8V, with standby and active currents of only 1μA and
NC 3
6 SCL
1mA respectively. The CW24C128/256 also has a page write
GND 4
5 SDA
capability for up to 64 bytes of data.
(Top View)
FEATURES
● Wide Voltage Operation VCC= 1.8V to 5.5V
● Low-power technology
- 1mA Active Current (Typical)
- 1μA Standby Current (Typical)
● Internally Organized:
- CW24C128, 16384x8 (128K bits)
- CW24C256, 32768x8 (256K bits)
● Two-wire Serial Interface, Fully I²C Bus Compatible
● 400kHz (1.8V, 2.7V, 5V) Compatibility
● Schmitt Trigger Inputs for Noise Suppression
● Write Protect Pin for Hardware Data Protection
● Self-timed Write Cycle (5 ms max)
● Byte and Multi-byte Write
● Page Write, 64-byte Page(CW24C128/256)
● Byte, Random and Sequential Read Mode
Automatic Address Increment
● ESD protection > 2.5kV
● High-reliability
- Endurance: 1 Million Write Cycles
- Data Retention: 100 Years
DIP8LˈSOP8LPackages
Pb-free finish available, RoHS compliant
APPLICATIONS
● Intelligent Instrument
Industrial Controller
● Household Appliance
● Automotive Electronics
● Computer/Notebook
● Communication
1






CW24C128 Datasheet, Funktion
CW24C128/CW24C256
PIN DESCRIPTION
No. Name
Function Description
1 A0 Address input. The A1 and A0 pins are device address inputs for hard wire
addressing and a total of eight CW24C128/256 devices may be addressed
2 A1 on a single bus system (device addressing is discussed in detail under the
3 NC Device Addressing section).
Serial address and data I/O. The SDA pin is bi-directional for serial data
5 SDA transfer. It is an open-drain pin, therefore the SDA bus requires a pull-up
resistor to VCC (typical 10kΩ).
Serial clock input. The SCL input is used to synchronize the data transfer to
6 SCL and from each EEPROM device. It’s positive edge clock data into the device
and negative edge clock data out of the device.
Write protect. The WP pin that provides hardware data protection. The WP pin
allows normal read/write operations when connected to ground (GND). When
7 WP the WP pin is connected to VCC, the write protection feature is enabled and
read only.
4 GND Circuit ground pin.
8 VCC Positive supply voltage.
MEMORY ORGANIZATION
Device
CW24C128
Total bits
128K
CW24C256
256K
Total pages
256
512
Bytes per page
64
64
Word address
14-bit
15-bit
DETAILED OPERATING INFORMATION
I²C DATA BUS AND TRANSMISSION PROTOCOL
I²C-Bus Interface
The CW24CXX supports I²C-bus transmission protocol. The I²C-bus is a bidirectional, two-
line communication interface. The two lines are a serial data line (SDA) and a serial clock line
(SCL). Both lines must be connected to a positive supply via a pull-up resistor. A typical bus
configuration using this 2-wire protocol is show in Figure 4.
SDA
SCL
VCC
RP RP
2-WIRE SERIAL
DATA BUS
MPU
CW24Cxx
PERIPHERAL
Figure 4. Typical 2-Wire Bus Configuration
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CW24C128 pdf, datenblatt
CW24C128/CW24C256
DETAILED OPERATING INFORMATION(CONTINUED)
3. Sequential Read
Sequential reads are initiated by either a current address read or a random address read.
After the microcontroller receives a data word, it responds with an acknowledgement. As long
as the EEPROM receives an acknowledgement, it will continue to increment the data word
address and serially clock out sequential data words. When the memory address limit is
reached, the data word address will "roll over" and the sequential read will continue. The
sequential read operation is terminated when the microcontroller does not respond with a "0"
but does generate a following stop condition (see Figure 14).
R
E
DEVICE A
ADDRESS D
DATA( n )
DATA( n+1 ) DATA( n+2 )
S
T
O
DATA( n+x ) P
SDA LINE
RA A A A
/C C C C
WK K K K
Figure 14. Sequential Read
N
O
A
C
K
TYPICAL APPLICATION
Vcc
U1 CW24C128
A0
1
VCC
8
A1
2
SCL
6
NC
3
SDA
5
GND WP
47
Device Address 0xA2
U2 CW24C128
Vcc
A0
1
VCC
8
A1
2
SCL
6
NC
3
SDA
5
GND WP
47
Device Address 0xA0
R1 R2
10K 10K
SCL
SDA
Figure 15. Cascades of Two EEPROM
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