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IX2113 Schematic ( PDF Datasheet ) - IXYS

Teilenummer IX2113
Beschreibung 600V High and Low Side Gate Driver
Hersteller IXYS
Logo IXYS Logo 




Gesamt 13 Seiten
IX2113 Datasheet, Funktion
INTEGRATED CIRCUITS DIVISION
IX2113
600V High and Low Side
Gate Driver
Driver Characteristics
Parameter
Rating
VOFFSET
IO +/- (Source/Sink)
VOUT
ton/toff
Delay Matching (Max)
600
2/2
10-20
113/100
20
Units
V
A
V
ns
ns
Features
Floating Channel for Bootstrap Operation to +600V
with Absolute Maximum Rating of +700V
Outputs Capable of Sourcing and Sinking 2A
Gate Drive Supply Range From 10V to 20V
Enhanced Robustness due to SOI Process
Tolerant to Negative Voltage Transients:
dV/dt Immune
3.3V Logic Compatible
Undervoltage Lockout for Both High-side and
Low-Side Outputs
Matched Propagation Delays
IX2113 Functional Block Diagram
Description
The IX2113 is a high voltage integrated circuit that can
drive high speed MOSFETs and IGBTs that operate at
up to +600V. The IX2113 is configured with
independent high-side and low-side referenced output
channels, both of which can source and sink 2A. The
floating high-side channel can drive an N-channel
power MOSFET or IGBT 600V from the common
reference.
Manufactured on IXYS Integrated Circuits Division's
proprietary high-voltage BCDMOS on SOI (silicon on
insulator) process, the IX2113 is extremely robust, and
is virtually immune to negative transients. The UVLO
circuit prevents the turn-on of the MOSFET or IGBT
until there is sufficient VBS or VCC supply voltage.
Propagation delays are matched for use in high
frequency applications.
The IX2113 is available in a 14-pin DIP package and
in a 16-pin SOIC package.
Ordering Information
Part
IX2113G
IX2113B
IX2113BTR
Description
14-Pin DIP (25/Tube)
16-Pin SOIC (50/Tube)
16-Pin SOIC (1000/Reel)
VDD
Level
VB
Shift High UVLO
HIN
Input Control Logic
&
VDD / VCC
VSS / COM
Pulse
Generator
Voltage
Level
Shift
RR
Q
S
Buffer
HO
SD Cycle-by-Cycle
Edge-Triggered
Shutdown
LIN
UVLO
VS
VCC
Level
VSS
Shift
VDD / VCC
VSS / COM
LS Delay
Control
Buffer
LO
COM
DS-IX2113-R03
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1






IX2113 Datasheet, Funktion
INTEGRATED CIRCUITS DIVISION
1.9 Test Waveforms
1.9.1 Switching Time Test Circuit
VCC=15V
10µF
HIN
SD
LIN
0.1µF 11 3
12
13
14
15 2
VB
7+
0.1µF
10µF 15V
6
8
CL
HO
- VS
(0 to 500V/600V)
10µF
1 LO
CL
Note: Pin numbers shown
are for the SOIC package.
IX2113
1.9.2 Input/Output Timing Diagram
HIN
LIN
SD
HO
LO
1.9.3 Switching Time Waveform Definition
HIN
LIN
ton
HO
LO
50%
50%
t
r
90%
toff tf
90%
10%
10%
1.9.4 Shutdown Waveform Definitions
50%
SD
tsd
HO 90%
LO
1.9.5 Delay Matching Waveform Definitions
HIN 50%
LIN
50%
LO HO
10%
MT MT
90%
LO HO
6
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R03

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IX2113 pdf, datenblatt
INTEGRATED CIRCUITS DIVISION
3.5 Mechanical Dimensions
3.5.1 IX2113B: 16-Pin SOIC Package
PIN 16
10.211 ± 0.254
(0.402 ± 0.010)
PIN 1
1.270 TYP
(0.050 TYP)
2.337 ± 0.051
(0.092 ± 0.002)
Recommended PCB Land Pattern
1.27
(0.050)
10.312 ± 0.381
(0.406 ± 0.015)
7.493 ± 0.127
(0.295 ± 0.005)
2.00
(0.079)
9.40
(0.370)
0.406 ± 0.076
(0.016 ± 0.003)
0.60
(0.024)
45º
IX2113
0.649 ± 0.102 0.203 ± 0.102 0.889 ± 0.178
(0.026 ± 0.004) (0.008 ± 0.004) (0.035 ± 0.007)
NOTES:
1. Coplanarity = 0.1016 (0.004) max.
2. Leadframe thickness does not include solder plating (1000 microinch maximum).
0.254 / +0.051 / -0.025
(0.010 / +0.002 / -0.001)
DIMENSIONS
mm
(inches)
3.5.2 IX2113BTR: Tape & Reel Packaging for 16-Pin SOIC Package
330.2 DIA.
(13.00 DIA.)
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
Embossed Carrier
Embossment
B0=10.70
(0.421)
K0=3.20
(0.126)
K1=2.70
(0.106)
A0=10.90
(0.429)
P=12.00
(0.472)
NOTES:
1. All dimensions carry tolerances of EIA Standard 481-2
2. The tape complies with all “Notes” for constant dimensions
listed on page 5 of EIA-481-2
W=16
(0.630)
Dimensions
mm
(inches)
12
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R03

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