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CXD4103R Schematic ( PDF Datasheet ) - SONY

Teilenummer CXD4103R
Beschreibung Signal Processor LSI for Single CCD Color Camera
Hersteller SONY
Logo SONY Logo 




Gesamt 30 Seiten
CXD4103R Datasheet, Funktion
Signal Processor LSI for Single CCD Color Camera
Distribution Internal Outside
Restraint
Limited Limited
CXD4103R
Description
The CXD4103R is a signal processor LSI for Ye, Cy, Mg and G single CCD color cameras. In addition to basic
camera signal processing functions, it includes an AE/AWB detection circuit, a sync signal generation circuit
and an external sync circuit, etc. This chip also has a built-in microcontroller to realize basic camera control
functions such as AE/AWB without an external microcomputer.
(Applications : Industrial CCD cameras (Surveillance/FA/image input cameras), Multimedia CCD cameras
(Teleconferencing/personal computer cameras))
Features
‹ Generates timing pulses to drive the single CCD image sensor
Built-in H driver for CCD image sensor
Luminance/chroma signal processing
‹ Supports NTSC/PAL modes
‹ Supports 510H/760H system CCD image sensor
‹ Built-in 10-bit A/D converter
‹ Built-in EVR (3ch)
‹ Analog composite output
Built-in digital encoder
10-bit D/A converter output
‹ Digital output
Conforms to ITU-REC656 format
‹ Supports external sync functions
Built-in phase comparator
‹ Built-in AE/AWB detector
‹ Block control functions with a built-in microcontroller
AE/AWB/CLAMP/Blemish detection and compensation
‹ Peripheral IC control function
EEPROM communication control
‹ Serial communication function (2-mode selection)
Microcomputer communication/start-stop synchronous system communication (RS-232C)
‹ Blemish detection and compensation function
‹ Mirror inversion function
Limited Limited
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license
by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating
the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E05949-CR






CXD4103R Datasheet, Funktion
CXD4103R
Pin Description
Pin
No.
Symbol
I/O
Description
Power
supply
1 AVS0
GND
2 VRB
I A/D converter reference voltage (bottom) input.
3 SVS0
4 VIN
Sub GND
I A/D converter analog signal input.
Analog 1
5 VRT
I A/D converter reference voltage (top) input.
6 AVD0
Power supply for analog (3.3V).
7 DVDD0 Power supply for logic (1.8V).
8 DVSS0 GND
9 CSROM O EEPROM chip select output
10 CASI
I Serial data input for system communication.
11 CASO
O Serial data output for system communication.
12 CASCK O Serial clock output for system communication.
13 XRST
I Reset input.
14 TEST1
15 VDE0
I Test
Power supply for input/output (3.3V).
Logic 1
16 SIFSEL I Serial interface mode switching input. 0 : microcomputer (3 wires) 1 : RS-232C
17 XCS
I Chip select input for 3-wire serial interface. (when SIFSEL = 0)
18 SI
I Serial data input for 3-wire serial interface. (when SIFSEL = 0)
19 SO
O Serial data output for 3-wire serial interface. (when SIFSEL = 0)
20 SCK
I Serial clock input for 3-wire serial interface. (when SIFSEL = 0)
21 DVDD1 Power supply for logic (1.8V).
22 DVSS1 GND
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6 Page









CXD4103R pdf, datenblatt
CXD4103R
AC Characteristics
(Within the recommended operating range)
Classification
Item
Symbol
Reset input Minimum Low period of XRST pin reset operation TwRST
P0 to P15 output delay time against DCK
TpdP
S0 output delay time against DCK
Digital output
S1 output delay time against DCK
TpdS0
TpdS1
DCK output delay time against ECK
TpdDCK
SYNC block HD, VD, FLD and SYNC output delay time
sync output against ECK
TpdSY
SCK input pulse width (High period)
TwHSCK
SCK input pulse width (Low period)
TwLSCK
XCS input setup time against SCK
TsuXCS
XCS input hold time against SCK
ThXCS
Serial
SI input setup time against SCK
communication
I/O
SI input hold time against SCK
SO output transition time against XCS
(Hi-Z Data active)
TsuSI
ThSI
TzdSO
SO transition time against XCS
(Data active Hi-Z)
TdzSO
SO output delay time against SCK
TpdSO
Min.
500
0.4
0.4
0.4
7
10
580
580
0
0
0
0
Typ. Max. Unit
— — ns
20 ns
28 ns
30 ns
29 ns
45 ns
580 ns
580 ns
— — ns
— — ns
— — ns
— — ns
— — ns
— — ns
580 ns
- 12 -

12 Page





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