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5P49EE802 Schematic ( PDF Datasheet ) - Integrated Device Technology

Teilenummer 5P49EE802
Beschreibung Low-power Clock Generator
Hersteller Integrated Device Technology
Logo Integrated Device Technology Logo 




Gesamt 28 Seiten
5P49EE802 Datasheet, Funktion
VersaClock® Low-power Clock Generator
5P49EE802
DATASHEET
Description
The 5P49EE802 is a programmable clock generator intended
for low power, battery operated consumer applications. There
are four internal PLLs, each individually programmable,
allowing for up to eight different output frequencies. The
frequencies are generated from a single reference clock. The
reference clock can come from either a TCXO or fundamental
mode crystal. An additional 32kHz crystal oscillator is
available to provide a real time clock or non-critical
performance MHz processor clock.
The 5P49EE802 can be programmed through the use of the
I2C interfaces. The programming interface enables the device
to be programmed when it is in normal operation or what is
commonly known as in system programmable. An internal
EEPROM allows the user to save and restore the
configuration of the device without having to reprogram it on
power-up.
Each of the four PLLs has an 8-bit reference divider and a
11-bit feedback divider. This allows the user to generate four
unique non-integer-related frequencies. The PLL loop
bandwidth is programmable to allow the user to tailor the PLL
response to the application. For instance, the user can tune
the PLL parameters to minimize jitter generation or to
maximize jitter attenuation. Spread spectrum generation is
supported on one of the PLLs.
Spread spectrum generation is supported on one of the PLLs.
The device is specifically designed to work with display
applications to ensure that the spread profile remains
consistent for each HSYNC in order to reduce ROW noise. It
also may operate in standard spread spectrum mode.
There are total seven 8-bit output dividers. Outputs are
LVCMOS. The outputs are connected to the PLLs via the
switch matrix. The switch matrix allows the user to route the
PLL outputs to any output bank. This feature can be used to
simplify and optimize the board layout. In addition, each
output's slew rate and enable/disable function can be
programmed.
Target Applications
Smart Mobile Handset
Personal Navigation Device (PND)
Camcorder
DSC
Portable Game Console
Personal Media Player
Features
Four internal PLLs
Internal non-volatile EEPROM
Internal I2C EEPROM master interface
FAST (400kHz) mode I2C serial interfaces
Input Frequencies
– TCXO: 10 MHz to 40 MHz
– Crystal: 8 MHz to 30 MHz
– RTC Crystal: 32.768 kHz
Output Frequency Ranges: kHz to 120 MHz
Each PLL has an 8-bit reference divider and a 11-bit
feedback-divider
8-bit output-divider blocks
One of the PLLs support Spread Spectrum generation
capable of configuration to pixel rate, with adjustable
modulation rate and amplitude to support video clock with
no visible artifacts
I/O Standards:
– Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS
– 3 independent adjustable VDDO groups
Programmable Slew Rate Control
Programmable Loop Bandwidth Settings
Programmable output inversion to reduce bimodal jitter
Individual output enable/disable
Power-down/Sleep mode
– 10A max in power down mode
– 32kHz clock output active sleep mode
– 100A max in sleep mode
1.8V VDD Core Voltage
Available in 28 pin 4x4mm QFN packages
-40 to +85°C Industrial Temp operation
5P49EE802 REVISION P 04/01/16
1
©2016 Integrated Device Technology, Inc.






5P49EE802 Datasheet, Funktion
5P49EE802 DATASHEET
Spread Spectrum Generation (PLLB)
PLLB has spread spectrum generation capability, which users
have the option of turning on and off. Spread spectrum profile,
frequency, and spread are fully programmable (within limits).
The programmable spread spectrum generation parameters
are NC[10:0], MOD[12:0], and NSS[10:0] bits. To enable
spread spectrum, set SSENB_B=0.
The spread spectrum circuitry was specifically developed to
accommodate video display applications. The spread
modulation frequency can be defined to exactly equal the
horizontal line frequency (HSYNC)
NC[10:0]
These bits are used to determine the number of pulses per
spread spectrum cycle. For video applications, NC is the
number of pixels on the horizontal display row (or integer
multiple of displayed pixels in a row). By matching the spread
period to the screen, no tearing or “shimmer” will be apparent.
NC must be an even number to insure that the upward spread
transition has the same number of steps as the downward
spread transition.
For non-video applications, this can also be seen as the
number of clock cycles for a complete spread spectrum
period.
FMID = FVCO/8
NC = 640 (integer number of spread periods/screen)
MOD = (25MHz * 640)/(2 * 54MHz) = 160
NSS = (640/2)+(640/8)*(27.27MHz-26.73MHz)/27MHz = 321.
FMOD = 27MHz/640 = 11.8kHz.
Non-Video Example
FREF = 25MHz, FOUT = 27 MHz, 31.25kHz modulation rate,
center spread of ±1%. Find the necessary spread spectrum
register settings.
FMID = FVCO/ 8
FMOD = 31.25kHz = 50.625MHz/NC.
NC = 1620
MOD = (25MHz * 1620)/(2 * 50.625MHz) = 400
NSS = (1620/2)+(1620/8)*(27.27MHz-26.73MHz)/27MHz =
814.
MOD[12:0]
These bits relate the VCO frequency to the target average
spread output frequency (FMID).
FMID = (FVCO) / 8
FMAX = FMID + (SS% * FMID)
FMIN = FMID - (SS% * FMID)
MOD = (FREF* NC) / (2 * FMID)
NSS[10:0]
These bits control the amplitude of the spread modulation.
NSS = (NC / 2) + (NC / 8) * (FMAX - FMIN) / FMID
Modulation frequency:
FMOD = FMID / NC (Eq. 11)
Video Example
FREF = 27 MHz, FOUT = 27 MHz, 640 pixels per line, center
spread of ±1%. Using FVCO=432MHz, find the necessary
spread spectrum register settings.
VERSACLOCK® LOW-POWER CLOCK GENERATOR
6
REVISION P 04/01/16

6 Page









5P49EE802 pdf, datenblatt
5P49EE802 DATASHEET
I2C Bus DC Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIH
VIL
VHYS
IIN
VOL
Input HIGH Level
Input LOW Level
Hysteresis of Inputs
Input Leakage Current
Output LOW Voltage
VDD = 0V
IOL = 3 mA
0.7xVDDO1
0.05xVDDO1
5.5
0.3xVDDO1
±1.0
0.4
V
V
V
µA
V
I2C Bus AC Characteristics for Standard Mode
Symbol
FSCLK
tBUF
tSU:START
tHD:START
tSU:DATA
tHD:DATA
tOVD
CB
tR
tF
tHIGH
tLOW
tSU:STOP
Parameter
Serial Clock Frequency (SCL)
Bus free time between STOP and START
Setup Time, START
Hold Time, START
Setup Time, data input (SDA)
Hold Time, data input (SDA) 1
Output data valid from clock
Capacitive Load for Each Bus Line
Rise Time, data and clock (SDA, SCLK)
Fall Time, data and clock (SDA, SCLK)
HIGH Time, clock (SCLK)
LOW Time, clock (SCLK)
Setup Time, STOP
Min Typ Max Unit
0 100 kHz
4.7 µs
4.7 µs
4 µs
250 ns
0 µs
3.45 µs
400 pF
1000
ns
300 ns
4 µs
4.7 µs
4 µs
1) No activity is allowed on I2C lines until VDD>1.62V.
2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCLK
signal) to bridge the undefined region of the falling edge of SCLK.
VERSACLOCK® LOW-POWER CLOCK GENERATOR
12
REVISION P 04/01/16

12 Page





SeitenGesamt 28 Seiten
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