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H8S2392 Schematic ( PDF Datasheet ) - Hitachi

Teilenummer H8S2392
Beschreibung 16-Bit Single-chip Microcomputer
Hersteller Hitachi
Logo Hitachi Logo 




Gesamt 30 Seiten
H8S2392 Datasheet, Funktion
Hitachi 16-Bit Single-chip Microcomputer
H8S/2357 Series,
H8S/2357
H8S/2352
H8S/2390
H8S/2392
H8S/2394
H8S/2398
ADE-602-146C
Rev. 4.0
09/05/01
Hitachi, Ltd.
H8S/2357F-ZTATTM
H8S/2398F-ZTATTM
H8S/2396F-ZTATTM
H8S/2395F-ZTATTM
Hardware Manual






H8S2392 Datasheet, Funktion
Section Item
Revisions (See Manual for Details)
3.5 Memory
Map in Each
Operating
Mode
Figure 3-1 Memory Map in
Each Operating Mode
(H8S/2357, H8S/2352) (1)
Notes amended
Figure 3-5 Memory Map in
Each Operating Mode
(H8S/2396) (1)
Figure added
Figure 3-6 Memory Map in
Each Operating Mode
(H8S/2395) (1)
Figure added
Figure 3-7 Memory Map in
Each Operating Mode
(H8S/2398) (1)
Figure added
4.1.3
4.1.3 Exception Vector
Exception Table
Vector Table
Description amended/added and note added
5.1.2 Block Figure 5-1 Block Diagram of Internal interrupt source modified
Diagram
Interrupt Controller
5.2 Register 5.2.1 System Control
Descriptions Register (SYSCR)
Description added
5.6.3
Operation
(1) Selection of Interrupt
Source
Description modified
(3) Operation Order
Description modified
6.2 Register 6.2.1 Bus Width Control
Descriptions Register (ABWCR)
Notes modified
6.2.5 Bus
Control
Register L
(BCRL)
Bit 5–External Address
Enable (EAE)
Notes added
6.3.4
Advanced
Mode
Area 0
Description modified
6.8.2 Pin Table 6-8 Pin States in Idle Notes added
States in Idle Cycle
Cycle
6.9 Write Figure 6-36 Example of
Data Buffer Timing when Write Data
Function Buffer Function is Used
Notes added

6 Page









H8S2392 pdf, datenblatt
Section
Item
Revisions (See Manual for Details)
22.2 Usage 22.2 Usage Note
Note
Description amended
Figure 22-32 VCL Capacitor Description amended
Connection Method
All pages from All pages from 22.3
Added
22.3 Electrical Electrical Characteristics
Characteristics of F-ZTAT Versions
of F-ZTAT
(H8S/2398, H8S/2396, and
Versions
H8S/2395 ) (Preliminary) to
(H8S/2398, 22.5 Usage Note
H8S/2396, and
H8S/2395 )
(Preliminary) to
22.5 Usage
Note
22.3.6 Flash Table 22-21 Flash Memory Z for wait time after P bit setting, in programming,
Memory
Characteristics
amended, and notes added
Characteristics
22.6.3 AC Figure 22-78 Burst ROM Amended
Characteristics Access Timing (Two-State
Access)
Figure 22-79 Burst ROM Amended
Access Timing (One-State
Access)
A.2 Instruction A.2 Instruction Codes
Codes
MOV mnemonic description amended
B. Internal I/O B.1 Addresses
Register
Address H'FEDB added
Notes 7, 8, 9, and 10 added to SYSCR2 of address
H'FF42
Address H'FFAC added
FLASH addresses added
Notes added
H'FED5: Bus Control
Register L BCRL: Bus
Controller
Notes added
H'FEDB: RAM Emulation
Register RAMER: Bus
Controller
Added

12 Page





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