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PDF IA21140AF Data sheet ( Hoja de datos )
| Número de pieza | IA21140AF | |
| Descripción | PCI FAST ETHERNET LAN CONTROLLER | |
| Fabricantes | InnovASIC | |
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IA21140AF
Preliminary Data Sheet
PCI FAST ETHERNET LAN CONTROLLER
innovASIC
Features
• Form, Fit and Function Compatible with the DEC™ 21140AF
• Available in 144 Pin PQFP Package
• Integrated Ethernet controller with PCI bus interface
• Supports 10 Mb/s and 10/100 Mb/s network interface
• PCS and scrambler/descrambler circuitry on chip
• Supports multiple PCI features:
- Unlimited PCI burst
- PCI read multiple
- PCI write and invalidate
- PCI read line
- PCI 5.0V and 3.3V environments
• Multiple interrupt sources
• Contains two independent 3K FIFOs to minimize external memory additions
• Provides sleep or snooze low-power modes
• Interfaces with MicroWire™ Serial ROM
• Provides a JTAG test port with boundary scan function
• Complies with IEEE 802.3, ANSI 8802-3, and Ethernet standards
The IA21140AF is a "plug-and-play" drop-in replacement for the original IC. innovASIC produces
replacement ICs using its MILESTM, or Managed IC Lifetime Extension System, cloning technology. This
technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible
with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon
technology advances. MILESTM also verifies the clone against the original IC so that even the
"undocumented features" are duplicated. This data sheet documents all necessary engineering information
about the IA21140AF including functional and I/O descriptions, electrical characteristics, and applicable
timing.
Copyright © 2001
innovASIC
The End of Obsolescence™
ENG210010110 -00
Page 1 of 19
www.innovasic.com
Customer Support:
1-888-824-4184
1 page  
IA21140AF
Preliminary Data Sheet
PCI FAST ETHERNET LAN CONTROLLER
I/O Description
The following section provides a functional description of the I/O pins on the IA21140AF.
NAME
Vdd
Vdd_clamp
Vss
ad[31:0]
br_a[1:0]
br_ad[7:0]
br_ce_n
c_be_n[3:0]
devsel_n
frame_n
gep[7:0]
gnt_n
Idsel
int_n
Type
Description
P 3.3 volt input supply voltage.
P 5.0 volt reference for 5.0 volt signaling environments and 3.3 volt reference
for 3.3 volt signaling environments.
P Ground Pin
I/O The PCI address and data lines are multiplexed on the same PCI pins. During
the first clock cycle of a transaction, the 32 bits contain an address and during
subsequent clock cycles, they contain data. Both read and write bursts are
supported in master operation only. Big or Little Indian byte ordering can be
used.
O Address line bit 0 also carries in two consecutive address cycles (bits 16 and
17) in a 256KB configuration. Bit 1 also latches the boot ROM address and
control lines via two external latches.
I/O In the first of two consecutive address cycles, these multiplexed lines contain
the boot ROM address bits [7:2], oe_n, and we_n. The second cycle contains
boot ROM address bits [15:8]. Bits 7 through 0 contain data during the data
cycle. These lines are used to carry data to and from the external register.
O Enable pin for the Boot ROM or an external register. Pin has an internal 5 k O
pull-up resistor.
I/O Bus command and byte enable are multiplexed on the same PCI pins. These
bits provide the bus command during the address phase of the transaction.
They provide the byte enable during the data phase. Byte enable determines
which byte lines carry valid data. Bit 0 coincides with byte 0. Bit 1 coincides
with byte 1, etc.
I/O Indicates that the driving device has decoded its address as the target of the
current access. As an input, determines whether a device on the bus has
been selected.
I/O The IA21140AF bus master asserts this signal to indicate the beginning and
duration of a bus transaction access. Data transfer continues while this signal
is asserted. Deasserting this signal indicates the transaction is in the final
phase.
I/O These pins can be configured by software to perform either input or output
functions for system specific applications.
I Indicates to the IA21140AF that access to the bus has been granted.
I Used as a chip select by the host to indicate configuration read and write
cycles.
O/D When one of the appropriate bits in CSR5 gets set, interrupt request gets
asserted if the corresponding mask bit in CSR7 is not set. If more than one
interrupt bit in CSR5 is set and all input bits are not cleared, interrupt request
gets deasserted for one clock cycle. Interrupt request gets deasserted by
writing a “1” into the appropriate CSR5 bit. This pin must be pulled up by an
external resistor.
Copyright © 2001
innovASIC
The End of Obsolescence™
ENG210010110 -00
Page 5 of 19
www.innovasic.com
Customer Support:
1-888-824-4184
5 Page 
IA21140AF
Preliminary Data Sheet
PCI FAST ETHERNET LAN CONTROLLER
PCI Reset:
Timing Diagram
pci_clk
pci_rst
Internal
Reset
10 pci_clk cycles
33 pci_clk cycles
Timing Characteristics
Symbol Parameter
Trst pci_rst pulse width
Min Max
10 * Tcycle Not applicable
Conditions
pci_clk active
Copyright © 2001
innovASIC
The End of Obsolescence™
ENG210010110 -00
Page 11 of 19
www.innovasic.com
Customer Support:
1-888-824-4184
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet IA21140AF.PDF ] | |
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