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NLHV18T3244 Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer NLHV18T3244
Beschreibung 18-Channel Level Shifter
Hersteller ON Semiconductor
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Gesamt 10 Seiten
NLHV18T3244 Datasheet, Funktion
NLHV18T3244
18-Channel Level Shifter
The NLHV18T3244 is an 18channel level translator designed for
high voltage level shifting applications such as displays. The 18
channels are divided into twelve and two three channel groups, with
each group controlled by the inverting inputs SEL1, SEL2 and, SEL3;
respectively. The EN input is used to select the ‘ON’ or power saving
shutdown modes.
Each channel consists of a high voltage output buffer. The output
buffers use Nchannel low side and Pchannel high side transistors.
The output signal on pins OUT1 to OUT18 is pulled by the transistors
to the positive high or negative low voltage on the VHx and VLx power
supply pins, respectively, depending on the voltage of the inverting
pins.
Features
18 NonInverting / Inverting Channels
VH1, VH2 Supply Range: 5 V to 25 V
VL1, VL2 Supply Range: 13 V to 0 V
VHx – VLx Difference Range: 5 V to 25 V
VL1 and VL2 can be tied together or connected to independent supply
voltages as long as VL1 VL2
VD Supply Range: 2 V to 5.5 V
Outputs Specified with 1000 pF Capacitive Loads
Disable Function
Low Standby Current
No Glitch on PowerUp
Available in: 5 mm x 10 mm, 0.5 mm pitch, QFN50 Package
Typical Applications
OLED Drivers
High Voltage Level Shifters
Piezoelectric Motor Drivers
http://onsemi.com
MARKING
DIAGRAM
1 50
QFN50
CASE 485BW
NLHV
18T3244
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
May, 2013 Rev. 0
1
Publication Order Number:
NLHV18T3244/D






NLHV18T3244 Datasheet, Funktion
NLHV18T3244
ELECTRICAL CHARACTERISTICS (VHx =15 V, VLx = 5 V, VD = 2 to 5.5 V and EN = VD; unless otherwise specified)
405C to +855C
Symbol
Parameter
Parameter
Test Conditions
Min Typ Max
POWER SUPPLY
ID
Digital Supply Static
Enabled (EN = VD)
Current
Disabled (EN = 0 V),
(Power Down)
IN1 to IN18 = 0 V or
IN1 to IN18 = VD
2
5 10
IH1
Block 1 and 2 High
Voltage Supply Static
Enabled (EN = VD)
Current
Disabled (EN = 0 V),
(Power Down)
IN1 to IN18 = 0 V or
IN1 to IN18 = VD
2
5
IH2
Block 3 High Voltage
Supply Static Current
Enabled (EN = VD)
Disabled (EN = 0 V),
(Power Down)
IN1 to IN18 = 0 V or
IN1 to IN18 = VD
2
5
IL1
Block 1 and 2 Low
Voltage Supply Static
Current
Enabled (EN = VD)
Disabled (EN = 0 V),
(Power Down)
IN1 to IN18 = 0 V or
IN1 to IN18 = VD
2
5
IL2 Block 3 Low Voltage Enabled (EN = VD)
Supply Static Current Disabled (EN = 0 V),
(Power Down)
IN1 to IN18 = 0 V or
IN1 to IN18 = VD
2
5
VH1 HighSide DC Supply 1
VH2 HighSide DC Supply 2
VL1 LowSide DC Supply 1
VL1 VL2
VL1 must be the lowest voltage in all
conditions
5
5
13
15
17
5
25
25
0
VL2 LowSide DC Supply 2
VHx VL Differential VHx – VL Voltage
INPUT (IN1 – IN18, EN, SEL1 – SEL3)
VL1 5
5
0
25
VIH Logic ‘1’ Input Voltage
VIL Logic ‘0’ Input Voltage
IIH Logic ‘1’ Input Current
IIL Logic ‘0’ Input Current
CIN Input Capacitance
RIN Input Resistance
OUTPUT (OUT1 – OUT18)
VI = VIH
VI = VIL
TA = 25_C
TA = 25_C
0.7 x VD
0.3 x VD
0.1 10
0.1 10
3.5
50
VOH
VOL
VOUT High Voltage
VOUT Low Voltage
INx = 3.3 V, IL = 20 mA
INx = 0 V, IL = 20 mA
VHX0.2
VLX +
0.12
ROH
ROL
IPEAK
IOZ
ON Resistance, VH to OUTx
ON Resistance, VL to OUTx
Peak Output Current
Output Tristate Mode Leakage Current
IL = 20 mA
IL = 20 mA
CL = 1000 pF
INx = 3.3 V, VD = 3.3 V, EN = GND
5
5
1100
8.5
7.5
5
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
V
mA
mA
pF
MW
V
V
W
W
mA
mA
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