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PDF NCP1340 Data sheet ( Hoja de datos )
| Número de pieza | NCP1340 | |
| Descripción | Controller Featuring Valley Lock-Out Switching | |
| Fabricantes | ON Semiconductor | |
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NCP1340
Product Preview
High-Voltage,
Quasi-Resonant, Controller
Featuring Valley Lock-Out
Switching
The NCP1340 is a highly integrated quasi−resonant flyback
controller suitable for designing high−performance off−line power
converters. With an integrated active X2 capacitor discharge feature,
the NCP1340 can enable no−load power consumption below 30 mW.
The quasi−resonant current−mode flyback stage features a
proprietary valley−lockout circuitry, ensuring stable valley switching.
This system works down to the 6th valley and transitions to a
frequency foldback mode to reduce switching losses. As the load
decreases further, the NCP1340 enters quiet−skip mode to manage the
power delivery.
To help ensure converter ruggedness, the NCP1340 implements
several key protective features such as internal brownout detection, a
non−dissipative Over Power Protection (OPP) for constant maximum
output power regardless of input voltage, a latched over voltage and
NTC−ready overtemperature protection through a dedicated pin, and
line removal detection to safely discharge the X2 capacitors when the
line is removed.
If transient load capability is desired, the NCP1341 offers the same
performance and features with the addition of power excursion mode
(PEM).
Features
• Integrated High−Voltage Startup Circuit with Brownout Detection
• Integrated X2 Capacitor Discharge Capability
• Wide VCC Range from 9 V to 28 V
• 28 V VCC Overvoltage Protection
• Abnormal Overcurrent Fault Protection for Winding Short Circuit or
Saturation Detection
• Internal Temperature Shutdown
• Valley Switching Operation with Valley−Lockout for Noise−Free
Operation
• Frequency Foldback with 25 kHz Minimum Frequency Clamp for
Increased Efficiency at Light Loads
• Skip Mode with Quiet−Skip Technology for Highest Performance
During Light Loads
• Minimized Current Consumption for No Load Power Below 30 mW
• Frequency Jittering for Reduced EMI Signature
• Latching or Auto−Recovery Timer−Based Overload Protection
• Adjustable Overpower Protection
• Fixed or Adjustable Maximum Frequency Clamp
• Fault Pin for Severe Fault Conditions, NTC Compatible for OTP
• 4−ms Soft−Start Timer
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
www.onsemi.com
9
1
SOIC−9 NB
D SUFFIX
CASE 751BP
8
1
SOIC−8 NB
D SUFFIX
CASE 751
MARKING DIAGRAM
9
1340xz
ALYW
G
1
1340xz = Specific Device Code
x = A or B
z = 1, 2 or 3
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
PIN CONNECTIONS
1
Fault
HV
FMAX
FB
VCC
ZCD/OPP
DRV
CS GND
1
Fault
FB
ZCD/OPP
CS
(Top Views)
HV
VCC
DRV
GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. P1
1
Publication Order Number:
NCP1340/D
1 page  
NCP1340
Table 4. ELECTRICAL CHARACTERISTICS: (VCC = 12 V, VHV = 120 V, VFault = open, VFB = 2.4 V, VCS = 0 V, VZCD = 0 V, VFMAX
= 0 V, CVCC = 100 nF , CDRV = 1 nF, for typical values TJ = 25°C, for min/max values, TJ is – 40°C to 125°C, unless otherwise noted)
Characteristics
Conditions
Symbol
Min Typ Max Unit
START−UP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Discharge Voltage During Line Removal
Minimum Operating Voltage
Operating Hysteresis
Internal Latch / Logic Reset Level
Transition from Istart1 to Istart2
VCC(off) Delay
Startup Delay
Minimum Voltage for Start−Up Current
Source
dV/dt = 0.1 V/ms
VCC increasing
VCC decreasing
VCC decreasing
VCC(on) − VCC(off)
VCC decreasing
VCC increasing, IHV = 650 mA
VCC decreasing
Delay from VCC(on) to DRV Enable
VCC(on)
VCC(X2_reg)
VCC(off)
VCC(HYS)
VCC(reset)
VCC(inhibit)
tdelay(VCC_off)
tdelay(start)
VHV(MIN)
16.0
17.0
8.5
7.5
4.5
0.40
–
–
–
17.0
18.0
9.0
–
5.5
0.70
30.0
–
–
18.0
19.0
9.5
–
7.5
1.05
–
500
40
V
ms
ms
V
Inhibit Current Sourced from VCC Pin
Start−Up Current Sourced from VCC Pin
Start−Up Circuit Off−State Leakage Cur-
rent
Supply Current
Fault or Latch
Skip Mode (excluding FB current)
Operating Current
VCC Overvoltage Protection Threshold
VCC Overvoltage Protection Delay
X2 CAPACITOR DISCHARGE
Vcc = 0 V
Vcc = Vcc(on) – 0.5 V
VHV = 162.5 V
VHV = 325 V
VHV = 700 V
VCC = VCC(on) – 0.5 V
VFB = 0 V
fsw = 50 kHz, CDRV = open
Istart1
Istart2
IHV(off1)
IHV(off2)
IHV(off3)
0.2 0.5 0.65
2.4 3.75 5.0
– – 15
– – 20
– – 50
ICC1
ICC2
ICC3
VCC(OVP)
tdelay(VCC_OVP)
0.075
0.185
0.5
27
–
0.115
0.230
1.0
28
30.0
0.150
0.315
1.5
29
–
mA
mA
mA
mA
V
ms
Line Voltage Removal Detection Timer
Discharge Timer Duration
Line Detection Timer Duration
VCC Discharge Current
HV Discharge Level
BROWNOUT DETECTION
VCC = 20 V
tline(removal)
tline(discharge)
tline(detect)
ICC(discharge)
VHV(discharge)
65
21
21
13
–
100 135 ms
32 43 ms
32 43 ms
18 23 mA
– 30 V
System Start−Up Threshold
Brownout Threshold
Hysteresis
Brownout Detection Blanking Time
GATE DRIVE
VHV increasing
VHV decreasing
VHV increasing
VHV decreasing
VBO(start)
VBO(stop)
VBO(HYS)
tBO(stop)
107 112 116
V
93 98 102 V
9.0 14 – V
40 70 100 ms
Rise Time
Fall Time
Current Capability
Source
Sink
High State Voltage
Low Stage Voltage
FEEDBACK
VDRV from 10% to 90%
tDRV(rise)
– 40 80 ns
VDRV from 90% to 10%
tDRV(fall)
– 20 60 ns
IDRV(SRC)
IDRV(SNK)
mA
– 500 –
– 800 –
VCC = VCC(off) + 0.2 V, RDRV = 10 kW VDRV(high1)
8.0
–
–V
VCC = 30 V, RDRV = 10 kW
VDRV(high2)
10
12
14
VFault = 0 V
VDRV(low) – – 0.25 V
Open Pin Voltage
VFB to Internal Current Setpoint Division
Ratio
VFB(open)
KFB
4.9 5.0 5.1
−4−
V
–
Internal Pull−Up Resistor
VFB = 0.4 V
RFB 350 400 420 kW
www.onsemi.com
5
5 Page 
NCP1340
DRIVER
The NCP1340 maximum supply voltage, VCC(MAX), is
28 V. Typical high−voltage MOSFETs have a maximum
gate voltage rating of 20 V. The DRV pin incorporates an
active voltage clamp to limit the gate voltage on the external
MOSFETs. The DRV voltage clamp, VDRV(high) is typically
12 V with a maximum limit of 14 V.
REGULATION CONTROL
Peak Current Control
The NCP1340 is a peak current−mode controller, thus the
FB voltage sets the peak current flowing in the transformer
and the MOSFET. This is achieved by sensing the MOSFET
current across a resistor and applying the resulting voltage
ramp to the non−inverting input of the PWM comparator
through the CS pin. The current limit threshold is set by
applying the FB voltage divided by KFB (typically 4) to the
inverting input of the PWM comparator. When the current
sense voltage ramp exceeds this threshold, the output driver
is turned off, however, the peak current is affected by several
functions (see Figure 7):
The peak current level is clamped during the soft−start
phase. The setpoint is actually limited by a clamp level
ramping from 0 to 0.8 V within 4 ms.
In addition to the PWM comparator, a dedicated
comparator monitors the current sense voltage, and if it
reaches the maximum value, VILIM (typically 800 mV), the
gate driver is turned off and the overload timer is enabled.
This occurs even if the limit imposed by the feedback
voltage is higher than VILIM1. Due to the parasitic
capacitances of the MOSFET, a large voltage spike often
appears on the CS Pin at turn−on. To prevent this spike from
falsely triggering the current sense circuit, the current sense
signal is blanked for a short period of time, tLEB1 (typically
275 ns), by a leading edge blanking (LEB) circuit. Figure 7
shows the schematic of the current sense circuit.
The peak current is also limitied to a minimum level,
Vfreeze (0.2 V, typically). This results in higher efficiency at
light loads by increasing the minimum energy delivered per
switching cycle, while reducing the overall number of
switching cycles during light load.
Figure 7. Peak Current Setpoint
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11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet NCP1340.PDF ] | |
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