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NB3V60113G Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer NB3V60113G
Beschreibung 1.8V Programmable OmniClock Generator
Hersteller ON Semiconductor
Logo ON Semiconductor Logo 




Gesamt 20 Seiten
NB3V60113G Datasheet, Funktion
NB3V60113G
1.8 V Programmable
OmniClock Generator
with Single Ended (LVCMOS) and Differential
(LVDS/HCSL) Outputs
The NB3V60113G, which is a member of the OmniClock family, is
a one−time programmable (OTP), low power PLL−based clock
generator that supports any output frequency from 8 kHz to 200 MHz.
The device accepts fundamental mode parallel resonant crystal or a
single ended (LVCMOS) reference clock as input. It generates either
three single ended (LVCMOS) outputs, or one single ended output and
one differential (LVDS/HCSL) output. The output signals can be
modulated using the spread spectrum feature of the PLL
(programmable spread spectrum type, deviation and rate) for
applications demanding low electromagnetic interference (EMI).
Using the PLL bypass mode, it is possible to get a copy of the input
clock on any or all of the outputs. The device can be powered down
using the Power Down pin (PD#). It is possible to program the internal
input crystal load capacitance and the output drive current provided by
the device. The device also has automatic gain control (crystal power
limiting) circuitry which avoids the device overdriving the external
crystal.
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WDFN8
CASE 511AT
MARKING DIAGRAM
1
V0MG
G
V0 = Specific Device Code
M = Date Code
G = Pb−Free Device
(Note: Microdot may be in either location)
Features
Member of the OmniClock Family of Programmable Clock
Generators
Operating Power Supply: 1.8 V ± 0.1 V
I/O Standards
Inputs: LVCMOS, Fundamental Mode Crystal
Outputs: LVCMOS
Outputs: LVDS and HCSL
3 Programmable Single Ended (LVCMOS) Outputs
from 8 kHz to 200 MHz
1 Programmable Differential Clock Output up to
200 MHz
Input Frequency Range
Crystal: 3 MHz to 50 MHz
Reference Clock: 3 MHz to 200 MHz
Configurable Spread Spectrum Frequency Modulation
Parameters (Type, Deviation, Rate)
Programmable Internal Crystal Load Capacitors
Programmable Output Drive Current for Single Ended
Outputs
ORDERING INFORMATION
See detailed ordering and shipping information on page 19 of
this data sheet.
Power Saving mode through Power Down Pin
Programmable PLL Bypass Mode
Programmable Output Inversion
Programming and Evaluation Kit for Field
Programming and Quick Evaluation
Temperature Range −40°C to 85°C
Packaged in 8−Pin WDFN
These are Pb−Free Devices
Typical Applications
eBooks and Media Players
Smart Wearables, Portable Medical and Industrial
Equipment
Set Top Boxes, Printers, Digital Cameras and
Camcorders
© Semiconductor Components Industries, LLC, 2016
January, 2016 − Rev. 2
1
Publication Order Number:
NB3V60113G/D






NB3V60113G Datasheet, Funktion
NB3V60113G
Figure 5. Frequency Modulation or Spread Spectrum Clock for EMI Reduction
The outputs of the NB3V60113G can be programmed to
have either center spread from ±0.125% to ±3% or down
spread from −0.25% to −4%. The programmable step size
for spread spectrum deviation is 0.125% for center spread
and 0.25% for down spread respectively. Additionally, the
frequency modulation rate is also programmable.
Frequency modulation from 30 kHz to 130 kHz can be
selected. Spread spectrum, when on, applies to all the
outputs of the device but not to output clocks that use the
PLL bypass feature. There exists a tradeoff between the
input clock frequency and the desired spread spectrum
profile. For certain combinations of input frequency and
modulation rate, the device operation could be unstable and
should be avoided. For spread spectrum applications, the
following limits are recommended:
Fin (Min) = 6.75 MHz
Fmod (range) = 30 kHz to 130 kHz
Fmod (Max) = Fin / 225
For any input frequency selected, above limits must be
observed for a good spread spectrum profile.
For example, the minimum recommended reference
frequency for a modulation rate of 30 kHz would be 30 kHz
* 225 = 6.75 MHz. For 27 MHz, the maximum recommended
modulation rate would be 27 MHz / 225 = 120 kHz.
Control Inputs
Power Down
Power saving mode can be activated through the power
down PD# input pin. This input is an LVCMOS active Low
Master Reset that disables the device and sets outputs Low.
By default it has an internal pull−down resistor. The chip
functions are disabled by default and when PD# pin is pulled
high the chip functions are activated.
Configuration Space
NB3V60113G has one Configuration. Table 4 shows an
example of device configuration.
Table 4. EXAMPLE CONFIGURATION
Input
Frequency
Output Frequency
VDD
SS%
24 MHz
CLK0 = 33 MHz
CLK1 = 12 MHz
CLK2 = 24 MHz
1.8 V
−0.5%
SS Mod
Rate
100 kHz
Output Drive
CLK0 = 8 mA
CLK1 = 4 mA
CLK2 = 2 mA
Output
Inversion
CLK0 = N
CLK1 = N
CLK2 = Y
Output
Enable
CLK0 = Y
CLK1 = Y
CLK2 = Y
PLL Bypass
CLK0 = N
CLK1 = N
CLK2 = Y
Notes
CLK2 Ref clk
Default Device State
The NB3V60113G parts shipped from ON Semiconductor
are blank, with no inputs/outputs programmed. These need
to be programmed by the field sales or distribution or by the
user themselves before they can be used. Programmable
clock software downloadable from the ON Semiconductor
website can be used along with the programming kit to
achieve this purpose. For mass production, parts can be
programmed with a customer qualified configuration and
sourced from ON Semiconductor as a dash part number (Eg.
NB3V60113G−01).
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NB3V60113G pdf, datenblatt
NB3V60113G
SCHEMATIC FOR OUTPUT TERMINATION
Figure 6. Typical Termination for Single−Ended and Differential Signaling Device Load
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