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NB3H63143G Schematic ( PDF Datasheet ) - ON Semiconductor

Teilenummer NB3H63143G
Beschreibung Programmable Clock Generator
Hersteller ON Semiconductor
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Gesamt 24 Seiten
NB3H63143G Datasheet, Funktion
NB3H63143G
Programmable Clock
Generator with Single Ended
(LVCMOS/LVTTL) and
Differential (LVPECL/LVDS/
HCSL/CML) Outputs
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The NB3H63143G is a one−time programmable (OTP), low power
PLL−based clock generator that supports any output frequency from
8 kHz to 200 MHz. The device accepts fundamental mode parallel
resonant crystal or a single ended (LVCMOS/LVTTL) reference clock
as input. It generates either three single ended (LVCMOS/LVTTL)
1
QFN16
CASE 485AE
outputs, or one single ended output and one differential
(LVPECL/LVDS/HCSL/CML) output. The output signals can be
MARKING DIAGRAM
modulated using the spread spectrum feature of the PLL
(programmable spread spectrum type, deviation and rate) for
applications demanding low electromagnetic interference (EMI).
Individual output enable pins OE[2:0] are available to enable/disable
3H631
43Gxx
ALYWG
G
the outputs. Individual output voltage pins VDDO[2:0] are available
to independently set the output voltage of each output. Up to four
different configurations can be written into the device memory. Two
selection pins (SEL[1:0]) allow the user to select the configuration to
use. Using the PLL bypass mode, it is possible to get a copy of the
input clock on any or all of the outputs. The device can be powered
down using the Power Down pin (PD#). It is possible to program the
internal input crystal load capacitance and the output drive current
3H63143G
xx
A
L
Y
W
G
= Specific Device Code
= Specific Program Code (Default
‘00’ for Unprogrammed Part)
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
provided by the device. The device also has automatic gain control
(Note: Microdot may be in either location)
(crystal power limiting) circuitry which avoids the device overdriving
the external crystal.
Features
ORDERING INFORMATION
See detailed ordering and shipping information on page 23 of
this data sheet.
Operating Power Supply: 3.3 V ±10%, 2.5 V ±10%
I/O Standards
Programmable Output Drive Current for Single Ended
Inputs: LVCMOS/LVTTL, Fundamental Mode
Outputs
Crystal
Outputs: 1.8 V to 3.3 V LVCMOS/LVTTL
Outputs: LVPECL, LVDS, HCSL and CML
3 Programmable Single Ended (LVCMOS/LVTTL)
Outputs from 8 kHz to 200 MHz
1 Programmable Differential Clock Output up to
200 MHz
Input Frequency Range
Crystal: 3 MHz to 50 MHz
Power Saving Mode through Power Down Pin
Programmable PLL Bypass Mode
Programmable Output Inversion
Programming and Evaluation Kit Available for Field
Programming and Quick Evaluation
Temperature Range −40°C to 85°C
Packaged in 16−pin QFN
These are Pb−Free Devices
Reference Clock: 3 MHz to 200 MHz
Configurable Spread Spectrum Frequency Modulation
Typical Applications
eBooks and Media Players
Parameters (Type, Deviation, Rate)
Individual Output Enable Pins
Independent Output Voltage Pins
Smart Wearables, Smart Phones, Portable Medical and
Industrial Equipment
Set Top Boxes, Printers, Digital Cameras and
Programmable Internal Crystal Load Capacitors
Camcorders
© Semiconductor Components Industries, LLC, 2015
October, 2015 − Rev. 2
1
Publication Order Number:
NB3H63143G/D






NB3H63143G Datasheet, Funktion
NB3H63143G
Output Inversion
All output clocks of the NB3H63143G can be phase
inverted relative to each other. This feature can also be used
in conjunction with the PLL BYPASS mode.
Spread Spectrum Frequency Modulation
Spread spectrum is a technique using frequency
modulation to achieve lower peak electromagnetic
interference (EMI). It is an elegant solution compared to
techniques of filtering and shielding. The NB3H63143G
modulates the output of its PLL in order to “spread” the
bandwidth of the synthesized clock, decreasing the peak
amplitude at the center frequency and at the frequency’s
harmonics. This results in significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most clock generators. Lowering EMI by
increasing a signal’s bandwidth is called ‘spread spectrum
modulation’.
Figure 5. Frequency Modulation or Spread Spectrum Clock for EMI Reduction
The outputs of the NB3H63143G can be programmed to
have either center spread from ±0.125% to ±3% or down
spread from −0.25% to −4%. The programmable step size
for spread spectrum deviation is 0.125% for center spread
and 0.25% for down spread respectively. Additionally, the
frequency modulation rate is also programmable.
Frequency modulation from 30 kHz to 130 kHz can be
selected. Spread spectrum, when on, applies to all the
outputs of the device but not to output clocks that use the
PLL bypass feature. There exists a tradeoff between the
input clock frequency and the desired spread spectrum
profile. For certain combinations of input frequency and
modulation rate, the device operation could be unstable and
should be avoided. For spread spectrum applications, the
following limits are recommended:
Fin (Min) = 6.75 MHz
Fmod (range) = 30 kHz to 130 kHz
Fmod (Max) = Fin / 225
For any input frequency selected, the above limits must be
observed for a good spread spectrum profile.
For example, the minimum recommended reference
frequency for a modulation rate of 30 kHz would be
30 kHz * 225 = 6.75 MHz. For 27 MHz, the maximum
recommended modulation rate would be
27 MHz / 225 = 120 kHz
Control Inputs
Configuration Space Selection
The SEL[1:0] pins are used to select one of the
pre−programmed configurations statically or dynamically
while the device is powered on. These pins are 2−level
LVCMOS/LVTTL. Up to four configurations can be stored
in the memory space of the device. Clock outputs can be
independently enabled or disabled through the
configuration space. To have a given clock output enabled,
it must be enabled in both the configuration space and
through its respective output enable pin.
The PLL re−locking and stabilization time must be taken
into consideration when dynamically changing the
configurations. Table 6 shows an example of four
configurations.
Table 6. EXAMPLE CONFIGURATION SPACE SETTINGS
Configuration
Selection
Input
Frequency
Output
Frequency
VDD
VDDO
SS%
I
25 MHz
CLK0=100 MHz 3.3 V VDDO0=2.5 V
−0.5%
CLK1=8 kHz
VDDO1=1.8 V
CLK2=25 MHz
VDDO2=1.8 V
II
40 MHz
CLK0=125 MHz 3.3 V VDDO0=2.5 V ±0.25%
CLK1=40 MHz
VDDO1=1.8 V
CLK2=10 MHz
VDDO2=1.8 V
III
100 MHz
CLK0=100 MHz 3.3 V VDDO0=2.5 V
No SS
CLK1=100 MHz
VDDO1=1.8 V
CLK2=100 MHz
VDDO2=1.8 V
IV
25 MHz
CLK0=100 MHz 3.3 V
VDDO0=NA
−1%
CLK1=100 MHz
VDDO1=2.5 V
CLK2=48 MHz
VDDO2=3.3 V
SS Mod
Rate
110 kHz
30 kHz
NA
100 kHz
Output
Drive
CLK0=12mA
CLK1=8mA
CLK2=4mA
CLK0=4mA
CLK1=4mA
CLK2=4mA
CLK0=12mA
CLK1=8mA
CLK2=4mA
CLK2=16mA
Output
Inversion
CLK0=N
CLK1=N
CLK2=Y
CLK0=N
CLK1=N
CLK2=N
CLK0=N
CLK1=Y
CLK2=Y
CLK0=NA
CLK1=NA
CLK2=N
Output
Enable
CLK0=Y
CLK1=Y
CLK2=Y
CLK0=Y
CLK1=Y
CLK2=Y
CLK0=Y
CLK1=Y
CLK2=Y
CLK0=NA
CLK1=Y
CLK2=Y
PLL
Bypass
CLK0=N
CLK1=N
CLK2=Y
CLK0=N
CLK1=Y
CLK2=N
CLK0=Y
CLK1=Y
CLK2=Y
CLK0=NA
CLK1=N
CLK2=N
Notes
CLK2
Ref clk
CLK1
Ref clk
All Three
Outputs
are Ref
clks
CLK[1:0] is
Differential
Output
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NB3H63143G pdf, datenblatt
NB3H63143G
AC ELECTRICAL CHARACTERISTICS (continued)(VDD = 3.3 V ±10%, 2.5 V ±10%, VDDO[2:0] = 3.3 V ± 10%, 2.5 V ± 10%, 1.8 V
± 0.1 V; VDDO VDD, GND = 0 V, TA = −40°C to 85°C, Notes 19, 20, 23, 24 and 25)
Symbol
Parameter
Condition
Min Typ Max Unit
SINGLE ENDED OUTPUTS (VDD = 3.3 V ±10%, 2.5 V ± 10%, VDDO[2:0] = 3.3 V ± 10%, 2.5 V ± 10%, 1.8 V ± 0.1V; VDDO VDD, TA =
−40 to 85°C) (Notes 19, 20, 23, 24 and 25)
tJITTER−3.3 V Period Jitter Peak−to−Peak
25 MHz xtal input, fout = 100 MHz,
SS off, Configuration Dependent
(Note 25, see Figure 14)
100 ps
Cycle−Cycle Jitter
25 MHz xtal input, fout = 100 MHz,
SS off, Configuration Dependent
(Note 25, see Figure 14)
100
tJITTER−2.5 V Period Jitter Peak−to−Peak
25 MHz xtal input, fout = 100 MHz,
SS off, Configuration Dependent
(Note 25, see Figure 14)
100 ps
Cycle−Cycle Jitter
25 MHz xtal input, fout = 100 MHz,
SS off, Configuration Dependent
(Note 25, see Figure 14)
100
tr / tf 3.3 V
Rise/Fall Time
Measured between 20% to 80% with
15 pF load, fout = 100 MHz,
VDD = VDDO = 3.3 V,
Max Drive
Min Drive
1
2
ns
tr / tf 2.5 V
Rise/Fall Time
Measured between 20% to 80% with
15 pF load, fout = 100 MHz,
VDD = VDDO = 2.5 V,
Max Drive
Min Drive
1
2
ns
tDC Output Clock Duty Cycle
VDD = 3.3 V, 2.5 V; VDDO VDD
Duty Cycle of Ref clock is 50%
%
PLL Clock
45
50
55
Reference Clock
40
50
60
DIFFERENTIAL OUTPUT (CLK1, CLK0) (VDD = 3.3 V ±10%, 2.5 V ± 10%, VDDO[2:0] = 3.3 V ± 10%, 2.5 V ± 10%, 1.8 V ± 0.1V; VDDO
VDD, TA = −40 to 85°C) (Notes 19, 20, 23, 24 and 25)
tJITTER−3.3 V Period Jitter Peak−to−Peak
Configuration Dependent. 25 MHz xtal
input, fout = 100 MHz, SS off, CLK2 =
OFF (Note 21, 23 and 25, see
Figure 14)
100
ps
Cycle−Cycle Jitter
Configuration Dependent. 25 MHz xtal
input, fout = 100 MHz, SS off, CLK2 =
OFF (Note 22, 23 and 25, see
Figure 14)
100
tJITTER−2.5 V Period Jitter Peak−to−Peak
Configuration Dependent. 25 MHz xtal
input, fout = 100 MHz, SS off, CLK2 =
OFF (Note 22 and 24, see Figure 9)
100
ps
Cycle−Cycle Jitter
Configuration Dependent. 25 MHz xtal
input, fout = 100 MHz, SS off, CLK2 =
OFF (Note 22, 23 and 25, see
Figure 14)
100
tr 3.3 V
Rise Time
Measured between 20% to 80%,
VDD = 3.3 V
LVPECL
LVDS
HCSL
CML
175
700 ps
tr 2.5 V
Rise Time
Measured between 20% to 80%,
VDD = 2.5 V
LVPECL
LVDS
HCSL
CML
175
700 ps
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