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7MBP50TEA120 Schematic ( PDF Datasheet ) - Fuji Electric

Teilenummer 7MBP50TEA120
Beschreibung IGBT
Hersteller Fuji Electric
Logo Fuji Electric Logo 




Gesamt 23 Seiten
7MBP50TEA120 Datasheet, Funktion






7MBP50TEA120 Datasheet, Funktion
4. Absolute Maximum Ratings
Tc=25°C unless otherwise specified.
Items
Symbol Min.
Max.
Units
Bus Voltage
(between terminal P and N)
DC
Surge
Short operating
VDC
VDC(surge)
Vsc
0
0
400
900
1000
800
V
V
V
Collector-Emitter Voltage *1
Vces
0
1200
V
DC Ic - 50 A
Collector Current
1ms
Icp - 100 A
Duty=100% *2 -Ic - 50 A
Collector Power Dissipation One transistor *3
Pc
- 287 W
Collector Current
DC
1ms
Ic - 15 A
Icp - 30 A
Forward Current Diode
IF - 15 A
Collector Power Dissipation One transistor *3
Pc
- 139 W
Supply Voltage of Pre-Driver *4
Vcc -0.5 20
V
Input Signal Voltage *5
Vin
-0.5 Vcc+0.5
V
Input Signal Current
Iin - 3 mA
Alarm Signal Voltage *6
VALM
-0.5
Vcc
V
Alarm Signal Current *7
ALM
-
20 mA
Junction Temperature
Tj - 150 °C
Operating Case Temperature
Topr -20 100 °C
Storage Temperature
Tstg -40 125 °C
Solder Temperature *8
Tsol - 260
Isolating Voltage
(Terminal to base, 50/60Hz sine wave 1min.)
Viso
-
AC2500
V
Screw Torque
Mounting (M5) - - 3.5 Nm
Note
*1 : Vces shall be applied to the input voltage between terminal P and U or or W or DB,
N and U or V or W or DB.
*2 : 125°C/FWD Rth(j-c)/(Ic×VF MAX)=125/0.86/(50×2.0)×100=100%
*3 : Pc=125°C/IGBT Rth(j-c)=125/0.44=287W [Inverter]
Pc=125/IGBT Rth(j-c)=125/0.90=139W [Brake]
*4 : VCC shall be applied to the input voltage between terminal No.4 and 1, 8 and 5,
12 and 9, 14 and 13
*5 : Vin shall be applied to the input voltage between terminal No.3 and 1, 7 and 5, 11 and 9,
16,17,18 and 13.
*6 : VALM shall be applied to the voltage between terminal No.2 and 1, No6 and 5,
No10 and 9, No.19 and 13.
*7 : IALM shall be applied to the input current to terminal No.2,6,10 and 19
*8 : Immersion time 10±1sec.
MS6M 00746
6a
23
H04-004-03

6 Page









7MBP50TEA120 pdf, datenblatt
11. Cautions for design and application 設計・適用上の注意点
1. Trace routing layout should be designed with particular attention to least stray capacity
between the primary and secondary sides of optical isolators by minimizing the wiring
length between the optical isolators and the IPM input terminals as possible.
フォトカプラとIPMの入力端子間の配線は極力短くし、フォトカプラの一次側と二次側の浮遊容量を小さくした
パターンレイアウトにして下さい。
2. Mount a capacitor between Vcc and GND of each high-speed optical isolator as close to
as possible.
高速フォトカプラのVcc-GND間に、コンデンサを出来るだけ近接して取り付けて下さい。
3. For the high-speed optical isolator, use high-CMR type one with tpHL, tpLH 0.8µs.
高速フォトカプラは、tpHL,tpLH0.8us、高CMRタイプをご使用ください。
4. For the alarm output circuit, use low-speed type optical isolators with CTR 100%.
アラーム出力回路は、低速フォトカプラCTR100%のタイプをご使用ください。
5. For the control power Vcc, use four power supplies isolated each. And they should be
designed to reduce the voltage variations.
制御電源Vccは、絶縁された4電源を使用してください。また、電圧変動を抑えた設計として下さい。
6. Suppress surge voltages as possible by reducing the inductance between the DC bus P
and N, and connecting some capacitors between the P and N terminals.
P-N間の直流母線は出来るだけ低インダクタンス化し、P-N端子間にコンデンサを接続するなどしてサージ
電圧を低減して下さい。
7. To prevent noise intrusion from the AC lines, connect a capacitor of some 4700pF between
the three-phase lines each and the ground.
ACラインからのノイズ侵入を防ぐために、3相各線-アース間に4700pF程のコンデンサを接続して下さい。
8. At the external circuit, never connect the control terminal GNDU to the main terminal
U-phase, GNDV to V-phase, GNDW to W-phase, and GND to N-phase. Otherwise,
malfunctions may be caused.
制御端子GNDUと主端子U相、制御端子GNDVと主端子V相、制御端子GNDWと主端子W相、
制御端子GNDと主端子Nを外部回路で接続しないで下さい。誤動作の原因になります。
9. Take note that an optical isolator’s response to the primary input signal becomes slow
if a capacitor is connected between the input terminal and GND.
入力端子-GND間にコンデンサを接続すると、フォトカプラ一次側入力信号に対する応答時間が長くなります
のでご注意ください。
10. Taking the used isolator’s CTR into account, design with a sufficient allowance to decide the
primary forward current of the optical isolator.
フォトカプラの一次側電流は、お使いのフォトカプラのCTRを考慮し十分に余裕をもった設計にして下さい。
MS6M 00746
12
23
a
H04-004-03

12 Page





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