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Número de pieza FAN6754WAMRMY
Descripción Highly Integrated Green-Mode PWM Controller
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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Febuary 2013
FAN6754WA
Highly Integrated Green-Mode PWM Controller
Brownout and VLimit Adjustment by HV Pin
Features
High-Voltage Startup
AC Input Brownout Protection with Hysteresis
Monitor HV to Adjust VLimit
Low Operating Current: 1.5 mA
Linearly Decreasing PWM Frequency to 22 kHz
Frequency Hopping to Reduce EMI Emission
Fixed PWM Frequency: 65 kHz
Peak-Current-Mode Control
Cycle-by-Cycle Current Limiting
Leading-Edge Blanking (LEB)
Internal Open-Loop Protection
GATE Output Maximum Voltage Clamp: 13 V
VDD Under-Voltage Lockout (UVLO)
VDD Over-Voltage Protection (OVP)
Programmable Over-Temperature Protection (OTP)
Internal Latch Circuit (OVP, OTP)
Open-Loop Protection (OLP); Restart for
FAN6754WAMRMY, Latch for FAN6754WAMLMY
SENSE Short-Circuit Protection (SSCP)
Built-in 8 ms Soft-Start Function
Applications
General-purpose switch-mode power supplies (SMPS)
and flyback power converters, including:
Power Adapters
Description
The highly integrated FAN6754WA PWM controller
provides several features to enhance the performance
of flyback converters. To minimize standby power
consumption, a proprietary Green-Mode function
provides off-time modulation to continuously decrease
the switching frequency under light-load conditions.
Under zero-load and very light-load conditions,
FAN6754WA saves PWM pulses by entering "deep"
Burst Mode. Burst Mode enables the power supply to
meet international power conservation requirements.
FAN6754WA also integrates a frequency-hopping
function that helps reduce EMI emission of a power
supply with minimum line filters. The built-in
synchronized slope compensation helps achieve stable
peak-current control. To keep constant output power
limit over universal AC input range, the current limit is
adjusted according to AC line voltage detected by the
HV pin. The gate output is clamped at 13 V to protect
the external MOSFET from over-voltage damage.
Other protection functions include AC input brownout
protection with hysteresis, sense pin short-circuit
protection, and VDD over-voltage protection. For over-
temperature protection, an external NTC thermistor can
be applied to sense the external switchers temperature.
When VDD OVP or OTP are activated, an internal latch
circuit is used to latch-off the controller. The Latch Mode
is reset when the VDD supply is removed.
FAN6754WA is available in an 8-pin SOP package.
Ordering Information
Part Number
FAN6754WAMRMY
FAN6754WAMLMY
Operating
Temperature Range
Package
-40 to +105°C
8-Pin, Small Outline Package (SOP)
Packing Method
Tape & Reel
© 2011 Fairchild Semiconductor Corporation
FAN6754WA • Rev. 1.0.6
1
www.fairchildsemi.com

1 page




FAN6754WAMRMY pdf
Electrical Characteristics
VDD=15 V and TA=25C unless otherwise noted.
Symbol
Parameter
Condition
VDD Section
VOP Continuously Operating Voltage
VDD-ON Start Threshold Voltage
VDD-OFF
VDD-OLP
VDD-LH
Minimum Operating Voltage
IDD-OLP Off Voltage
Threshold Voltage on VDD Pin for
Latch-Off Release Voltage
VDD-AC
Threshold Voltage on VDD Pin for
Disable AC Recovery to Avoid
Startup Failed
IDD-ST Startup Current
VDD-ON – 0.16 V
IDD-OP1
Operating Supply Current,
PWM Operation
VDD=20 V, FB=3 V Gate
Open
IDD-OP2
Operating Supply Current,
Gate Stop
VDD=20 V, FB=3 V
Operating Current at PWM-Off
ILH Phase Under Latch-Off
Conduction
VDD=5 V
IDD-OLP
Internal Sink Current Under Latch-
Off Conduction
VDD-OLP+0.1 V
VDD-OVP
tD-VDDOVP
VDD Over-Voltage Protection
VDD Over-Voltage Protection
Debounce Time
HV Section
IHV Supply Current from HV Pin
VAC=90 V(VDC=120 V),
VDD=0 V
IHV-LC Leakage Current after Startup
VAC-OFF Brown-out Threshold
VAC-ON Brown-in Threshold
VAC
VAC-ON - VAC-OFF
HV=700 V, VDD=VDD-
OFF+1 V
DC Source Series
R=200 kto HV Pin
See Equation 1
DC Source Series
R=200 kto HV Pin
See Equation 2
DC Source Series
R=200 kto HV Pin
tS-CYCLE Line Voltage Sample Cycle
tH-TIME Line Voltage Hold Period
tD-AC-OFF PWM Turn-off Debounce Time
FB > VFB-N
FB < VFB-G
FB > VFB-N
FB < VFB-G
Min. Typ. Max. Unit
24
16 17 18
9 10 11
5.5 6.5 7.5
3.5 4.0 4.5
VDD-OFF
+2.8
VDD-OFF
+3.3
1.5
VDD-OFF
+3.8
30
2.0
1.0 1.5
V
V
V
V
V
V
µA
mA
mA
30 60 90 µA
170 200 230
24 25 26
75 165 255
µA
V
µs
2.0 3.5 5.0 mA
1 20 µA
92 102 112
V
104 114 124
V
6 12 18 V
220
µs
650
20 µs
65 75 85 ms
180 235 290 ms
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
FAN6754WA • Rev. 1.0.6
5
www.fairchildsemi.com

5 Page





FAN6754WAMRMY arduino
Functional Description
Startup Current
For startup, the HV pin is connected to the line input
through an external diode and resistor; RHV, (1N4007 /
200 krecommended). Peak startup current drawn
from the HV pin is (VAC× 2 ) / RHV and charges the hold-
up capacitor through the diode and resistor. When the
VDD capacitor level reaches VDD-ON, the startup current
switches off. At this moment, the VDD capacitor only
supplies the FAN6754WA to keep the VDD until the
auxiliary winding of the main transformer provides the
operating current.
Operating Current
Operating current is around 1.5 mA. The low operating
current enables better efficiency and reduces the
requirement of VDD hold-up capacitance.
Green-Mode Operation
The proprietary Green-Mode function provides off-time
modulation to reduce the switching frequency in light-
load and no-load conditions. VFB, which is derived from
the voltage feedback loop, is taken as the reference.
Once VFB is lower than the threshold voltage (VFB-N), the
switching frequency is continuously decreased to the
minimum Green-Mode frequency of around 22 kHz.
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the
SENSE pin. The PWM duty cycle is determined by this
current-sense signal and VFB, the feedback voltage.
When the voltage on the SENSE pin reaches around
VCOMP = (VFB–0.6)/4, the switch cycle is terminated
immediately. VCOMP is internally clamped to a variable
voltage around 0.46 V for low-line output power limit.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense-resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate driver.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at
17V and 10V, respectively. During startup, the hold-up
capacitor must be charged to 17 V through the startup
resistor to enable the IC. The hold-up capacitor
continues to supply VDD until the energy can be
delivered from auxiliary winding of the main transformer.
VDD must not drop below 10 V during startup. This
UVLO hysteresis window ensures that hold-up capacitor
is adequate to supply VDD during startup.
Gate Output / Soft Driving
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
13 V Zener diode to protect power MOSFET transistors
against undesirable gate over voltage. A soft driving
waveform is implemented to minimize EMI.
Soft-Start
For many applications, it is necessary to minimize the
inrush current at startup. The built-in 8ms soft-start
circuit significantly reduces the startup current spike and
output voltage overshoot.
Slope Compensation
The sensed voltage across the current-sense resistor is
used for peak-current-mode control and cycle-by-cycle
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillation.
FAN6754WA inserts a synchronized, positive-going,
ramp at every switching cycle.
Constant Output Power Limit
When the SENSE voltage across sense resistor RSENSE
reaches the threshold voltage, around 0.46 V for low-
line condition, the output GATE drive is turned off after a
small delay, tPD. This delay introduces an additional
current proportional to tPD • VIN / LP. Since the delay is
nearly constant, regardless of the input voltage VIN,
higher input voltage results in larger additional power.
Therefore, the maximum output power at high line is
higher than that of low line. To compensate this
variation for a wide AC input range, a power-limiter is
controlled by the HV pin to solve the unequal power-limit
problem. The power limiter is fed to the inverting input of
the current limiting comparator. This results in a lower
current limit at high-line inputs than at low-line inputs.
Brownout and Constant Power Limited by
the HV Pin
Unlike previous PWM controllers, the FAN6754WA HV
pin can detect the AC line voltage to perform brownout
protection and line compensation for power limit. Using
a fast diode and startup resistor to sample the AC line
voltage, the peak value refreshes and is stored in a
register at each sampling cycle. When internal update
time is met, this peak value is used for brownout and
current-limit level judgment. Equation (1) and (2)
calculate the level of brown-in or brownout converted to
RMS value. For power saving, FAN6754WA enlarges
the sampling cycle to lower the power loss from HV
sampling at light-load condition.
VAC-ON (RMS)
(
0.9V
(RHV 1.6) ) /
1.6
2
VAC- OFF (RMS)( 0.81V
(RHV 1.6) ) /
1.6
2
where RHV is in k.
(1)
(2)
© 2011 Fairchild Semiconductor Corporation
FAN6754WA • Rev. 1.0.6
11
www.fairchildsemi.com

11 Page







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