W631GG6KB Datasheet PDF - Winbond
| Part Number | W631GG6KB | |
| Description | 8M x 8 BANKS x 16-BIT DDR3 SDRAM | |
| Manufacturers | Winbond | |
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W631GG6KB
8M 8 BANKS 16 BIT DDR3 SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ...................................................................................................................5
2. FEATURES ...........................................................................................................................................5
3. ORDER INFORMATION .......................................................................................................................6
4. KEY PARAMETERS .............................................................................................................................7
5. BALL CONFIGURATION ......................................................................................................................8
6. BALL DESCRIPTION............................................................................................................................9
7. FUNCTIONAL DESCRIPTION............................................................................................................11
7.1 Basic Functionality ..............................................................................................................................11
7.2 RESET and Initialization Procedure ....................................................................................................11
7.2.1
Power-up Initialization Sequence .....................................................................................11
7.2.2
Reset Initialization with Stable Power ..............................................................................13
7.3 Programming the Mode Registers.......................................................................................................14
7.3.1
Mode Register MR0 .........................................................................................................16
7.3.1.1
Burst Length, Type and Order ................................................................................17
7.3.1.2
CAS Latency...........................................................................................................17
7.3.1.3
Test Mode...............................................................................................................18
7.3.1.4
DLL Reset...............................................................................................................18
7.3.1.5
Write Recovery .......................................................................................................18
7.3.1.6
Precharge PD DLL .................................................................................................18
7.3.2
Mode Register MR1 .........................................................................................................19
7.3.2.1
DLL Enable/Disable................................................................................................19
7.3.2.2
Output Driver Impedance Control ...........................................................................20
7.3.2.3
ODT RTT Values ....................................................................................................20
7.3.2.4
Additive Latency (AL) .............................................................................................20
7.3.2.5
Write leveling ..........................................................................................................20
7.3.2.6
Output Disable........................................................................................................20
7.3.3
Mode Register MR2 .........................................................................................................21
7.3.3.1
Partial Array Self Refresh (PASR) ..........................................................................22
7.3.3.2
CAS Write Latency (CWL) ......................................................................................22
7.3.3.3
Auto Self Refresh (ASR) and Self Refresh Temperature (SRT) .............................22
7.3.3.4
Dynamic ODT (Rtt_WR) .........................................................................................22
7.3.4
Mode Register MR3 .........................................................................................................23
7.3.4.1
Multi Purpose Register (MPR) ................................................................................23
7.4 No OPeration (NOP) Command..........................................................................................................24
7.5 Deselect Command.............................................................................................................................24
7.6 DLL-off Mode ......................................................................................................................................24
7.7 DLL on/off switching procedure...........................................................................................................25
7.7.1
DLL ―on‖ to DLL ―off‖ Procedure.......................................................................................25
Publication Release Date: Feb. 27, 2013
Revision A04
-1-
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W631GG6KB
1. GENERAL DESCRIPTION
The W631GG6KB is a 1G bits DDR3 SDRAM, organized as 8,388,608 words 8 banks 16 bits. This
device achieves high speed transfer rates up to 1866 Mb/sec/pin (DDR3-1866) for various
applications. W631GG6KB is sorted into the following speed grades: -11, -12, 12I, 12A, 12K -15, 15I,
15A and 15K. The -11 speed grade is compliant to the DDR3-1866 (13-13-13) specification. The -12,
12I, 12A and 12K speed grades are compliant to the DDR3-1600 (11-11-11) specification (the 12I
industrial grade which is guaranteed to support -40°C ≤ TCASE ≤ 95°C). The -15, 15I, 15A and 15K
speed grades are compliant to the DDR3-1333 (9-9-9) specification (the 15I industrial grade which is
guaranteed to support -40°C ≤ TCASE ≤ 95°C).
The automotive grade parts temperature, if offered, has two simultaneous requirements: ambient
temperature (TA) surrounding the device cannot be less than -40°C or greater than +95°C (for 12A
and 15A), +105°C (for 12K and 15K), and the case temperature (TCASE) cannot be less than -40°C or
greater than +95°C (for 12A and 15A), +105°C (for 12K and 15K). JEDEC specifications require the
refresh rate to double when TCASE exceeds +85°C; this also requires use of the high-temperature self
refresh option. Additionally, ODT resistance and the input/output impedance must be derated when
TCASE is < 0°C or > +85°C.
The W631GG6KB is designed to comply with the following key DDR3 SDRAM features such as
posted CAS#, programmable CAS# Write Latency (CWL), ZQ calibration, on die termination and
asynchronous reset. All of the control and address inputs are synchronized with a pair of externally
supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and
CK# falling). All I/Os are synchronized with a differential DQS-DQS# pair in a source synchronous
fashion.
2. FEATURES
Power Supply: VDD, VDDQ = 1.5V ± 0.075V
Double Data Rate architecture: two data transfers per clock cycle
Eight internal banks for concurrent operation
8 bit prefetch architecture
CAS Latency: 6, 7, 8, 9, 10, 11 and 13
Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable On-
The-Fly (OTF)
Programmable read burst ordering: interleaved or nibble sequential
Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received with data
Edge-aligned with read data and center-aligned with write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge, data and data mask are referenced to both edges of
a differential data strobe pair (double data rate)
Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command,
address and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Auto-precharge operation for read and write bursts
Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR)
Precharged Power Down and Active Power Down
Publication Release Date: Feb. 27, 2013
Revision A04
-5-
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| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ W631GG6KB.PDF Datasheet ] | |
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