|
|
Número de pieza | PI4GTL2002 | |
Descripción | 2-bit bidirectional low voltage translator | |
Fabricantes | Pericom Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de PI4GTL2002 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
No Preview Available ! PI4GTL2002
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2-bit bidirectional low voltage translator
Features
2-bit bidirectional translator
Less than 1.5 ns maximum propagation delay to
accommodate Standard mode and Fast mode I2C-
bus devices and multiple masters
Allows voltage level translation between 0.8V, 1.2
V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5 V buses, which
allows direct interface with GTL, GTL+,
LVTTL/TTL and 5 V CMOS levels
Provides bidirectional voltage translation with no
direction pin
Low 3.5 ohm
-state connection between input
and output ports provides less signal distortion
Supports hot insertion
5 V tolerant inputs
Flow through pin out for ease of printed-circuit
board trace routing
ESD protection exceeds 4KV HBM per JESD22-
A114
Package: UQFN1.6*1.6-8L, MSOP-8L,SOIC-8L
Description
The Gunning Transceiver Logic - Transceiver
Voltage Clamps (GTL-TVC) provide high-speed voltage
translation with low ON-state resistance and minimal
propagation delay. The GTL2002 provides 2 NMOS
pass transistors (Sn and Dn) with a common gate (GREF)
and a reference transistor (SREF and DREF). The device
allows bidirectional voltage translations between 0.8 V
and 5.0 V without use of a direction pin.
When the Sn or Dn port is LOW the clamp is in the
ON-state and a low resistance connection exists between
the Sn and Dn ports. Assuming the higher voltage is on
the Dn port, when the Dn port is HIGH, the voltage on
the Sn port is limited to the voltage set by the reference
transistor (SREF). When the Sn port is HIGH, the Dn
port is pulled to VCC by the pull-up resistors. This
functionality allows a seamless translation between
higher and lower voltages selected by the user, without
the need for directional control.
All transistors have the same electrical
characteristics and there is minimal deviation from one
output to another in voltage or propagation delay. This is
a benefit over discrete transistor voltage translation
solutions, since the fabrication of the transistors is
symmetrical. Because all transistors in the device are
identical, SREF and DREF can be located on any of the
other two matched Sn/Dn transistors, allowing for easier
board layout. The translator's transistors provide
excellent ESD protection to lower voltage devices and at
the same time protect less ESD-resistant devices.
Pin Configuration
MSOP-8L/SOIC-8L(Top View)
UQFN1.6*1.6-8L(Top View)
2016-01-0001
PT0579 01/27/16
1
1 page PI4GTL2002
2-bit bidirectional low voltage translator
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Figure.2 Load Circuit for Outputs
Application Information
For the bidirectional clamping configuration, higher voltage to lower voltage or lower voltage to higher voltage, the GREF
input must be connected to DREF and both pins pulled to HIGH side VCC through a pull-up resistor (typically 200 kΩ). A filter
capacitor on DREF is recommended. The processor output can be totem pole or open-drain (pull-up resistors may be required) and
the chip set output can be totem pole or open-drain (pull-up resistors are required to pull the Dn outputs to VCC). However, if
either output is totem pole, data must be unidirectional or the outputs must be 3-stateable and the outputs must be controlled by
some direction control mechanism to prevent HIGH-to-LOW contentions in either direction. If both outputs are open-drain, no
direction control is needed. The opposite side of the reference transistor (SREF) is connected to the processor core power supply
voltage. When DREF is connected through a 200 kΩ resistor to a 3.3 V to 5.5 V VCC supply and SREF is set between 0.8 V to
(VCC -1.5 V), the output of each Sn has a maximum output voltage equal to SREF and the output of each Dn has a maximum
output voltage equal to VCC.
2016-01-0001
PT0579 01/27/16
5
5 Page PI4GTL2002
2-bit bidirectional low voltage translator
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
SOIC-8(W)
2016-01-0001
PT0579 01/27/16
11
11 Page |
Páginas | Total 12 Páginas | |
PDF Descargar | [ Datasheet PI4GTL2002.PDF ] |
Número de pieza | Descripción | Fabricantes |
PI4GTL2002 | 2-bit bidirectional low voltage translator | Pericom Semiconductor |
Número de pieza | Descripción | Fabricantes |
SLA6805M | High Voltage 3 phase Motor Driver IC. |
Sanken |
SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |