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PDF 74HCT4094 Data sheet ( Hoja de datos )
| Número de pieza | 74HCT4094 | |
| Descripción | 8-stage shift-and-store bus register | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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74HC4094; 74HCT4094
8-stage shift-and-store bus register
Rev. 7 — 10 February 2016
Product data sheet
1. General description
The 74HC4094; 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a
storage register and 3-state outputs. Both the shift and storage register have separate
clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to
enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is
available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when
clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW
transition of the CP input to allow cascading when clock edges are slow. The data in the
shift register is transferred to the storage register when the STR input is HIGH. Data in the
storage register appears at the outputs whenever the output enable input (OE) is HIGH. A
LOW on OE causes the outputs to assume a high-impedance OFF-state. Operation of the
OE input does not affect the state of the registers. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
2. Features and benefits
Complies with JEDEC standard JESD7A
Input levels:
For 74HC4094: CMOS level
For 74HCT4094: TTL level
Low-power dissipation
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
Serial-to-parallel data conversion
Remote control holding register
1 page  
NXP Semiconductors
74HC4094; 74HCT4094
8-stage shift-and-store bus register
7. Functional description
Table 3.
Inputs
CP
Function table[1]
OE STR
LX
LX
HL
HH
HH
HH
D
X
X
X
L
H
H
Parallel outputs
QP0
QPn
ZZ
ZZ
NC NC
L QPn 1
H QPn 1
NC NC
Serial outputs
QS1
QS2
Q6S
NC
NC Q7S
Q6S
NC
Q6S
NC
Q6S
NC
NC Q7S
[1] At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs.
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= positive-going transition; = negative-going transition;
Z = HIGH-impedance OFF-state; NC = no change;
Q6S = the data in register stage 6 before the LOW to HIGH clock transition;
Q7S = the data in register stage 7 before the HIGH to LOW clock transition.
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Fig 7. Timing diagram
=VWDWH
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DDI
74HC_HCT4094
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 10 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
5 of 22
5 Page 
NXP Semiconductors
74HC4094; 74HCT4094
8-stage shift-and-store bus register
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HCT4094
tpd propagation CP to QS1; see Figure 8 [1]
delay
VCC = 4.5 V
- 23 39 -
49
-
59 ns
VCC = 5 V; CL = 15 pF
- 19 -
-
-
-
- ns
CP to QS2; see Figure 8 [1]
VCC = 4.5 V
- 21 36 -
45
-
54 ns
VCC = 5 V; CL = 15 pF
- 18 -
-
-
-
- ns
CP to QPn; see Figure 8 [1]
VCC = 4.5 V
- 25 43 -
54
-
65 ns
VCC = 5 V; CL = 15 pF
- 21 -
-
-
-
- ns
STR to QPn; see Figure 9 [1]
VCC = 4.5 V
- 22 39 -
49
-
59 ns
VCC = 5 V; CL = 15 pF
- 19 -
-
-
-
- ns
ten enable time OE to QPn; see Figure 11 [2]
VCC = 4.5 V
- 20 35 -
44
-
53 ns
tdis disable time OE to QPn; see Figure 11 [3]
VCC = 4.5 V
- 21 35 -
44
-
53 ns
tt transition QPn and QSn; see
time Figure 8
[4]
VCC = 4.5 V
tW pulse width CP HIGH or LOW;
see Figure 8
-
7 15
-
19
-
22 ns
VCC = 4.5 V
STR HIGH; see Figure 9
16 7 - 20 - 24
- ns
VCC = 4.5 V
tsu set-up time Dn to CP; see Figure 10
VCC = 4.5 V
CP to STR; see Figure 9
16 5 - 20 - 24
10 4 - 13 - 15
- ns
- ns
VCC = 4.5 V
th hold time Dn to CP; see Figure 10
VCC = 4.5 V
CP to STR; see Figure 9
20 9 - 25 - 30
40- 4 - 4
- ns
- ns
VCC = 4.5 V
fmax maximum CP; see Figure 8
frequency
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
0 4 -
0
-
0
- ns
30 80 - 24
-
20
- MHz
- 86 -
-
-
-
- MHz
74HC_HCT4094
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 10 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
11 of 22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet 74HCT4094.PDF ] | |
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