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PDF 74HCT4017 Data sheet ( Hoja de datos )
| Número de pieza | 74HCT4017 | |
| Descripción | Johnson decade counter | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
Rev. 5 — 3 February 2016
Product data sheet
1. General description
The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded
outputs (Q0 to Q9), an output from the most significant flip-flop (Q5-9), two clock inputs
(CP0 and CP1) and an overriding asynchronous master reset input (MR). The counter is
advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or a
HIGH-to-LOW transition at CP1 while CP0 is HIGH. When cascading counters, the Q5-9
output, which is LOW while the counter is in states 5, 6, 7, 8 and 9, can be used to drive
the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0 = Q5-9 =
HIGH; Q1 to Q9 = LOW) independent of the clock inputs (CP0 and CP1). Automatic code
correction of the counter is provided by an internal circuit: following any illegal code the
counter returns to a proper counting mode within 11 clock pulses. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
2. Features and benefits
Wide supply voltage range from 2.0 V to 6.0 V
Input levels:
For 74HC4017: CMOS level
For 74HCT4017: TTL level
Complies with JEDEC standard no. 7 A
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
1 page  
NXP Semiconductors
5. Pinning information
5.1 Pinning
4
4
4
4
4
4
4
*1'
+&
+&7
9&&
05
&3
&3
4
4
4
4
DDK
Fig 6. Pin configuration SO16 and (T)SSOP16
5.2 Pin description
Table 2.
Symbol
Q[0:9]
GND
Q5-9
CP1
CP0
MR
VCC
Pin description
Pin
3, 2, 4, 7, 10, 1, 5, 6, 9, 11
8
12
13
14
15
16
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
WHUPLQDO
LQGH[DUHD
+&
+&7
4
4
4
4
4
4
*1'
05
&3
&3
4
4
4
DDK
7UDQVSDUHQWWRSYLHZ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 7. Pin configuration DHVQFN16
Description
decoded output
ground (0 V)
carry output (active LOW)
clock input (HIGH-to-LOW edge-triggered)
clock input (LOW-to-HIGH edge-triggered)
master reset input (active HIGH)
supply voltage
74HC_HCT4017
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 3 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
5 of 23
5 Page 
NXP Semiconductors
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
Table 7. Dynamic characteristics …continued
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 11.
Symbol Parameter
Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
tt transition time see Figure 10
[2]
VCC = 4.5 V
- 7 15
-
19
-
22 ns
tW
pulse width
CP0 and CP1 (HIGH or
LOW); see Figure 9
VCC = 4.5 V
16 7 -
20
-
24
- ns
MR (HIGH); see Figure 9
VCC = 4.5 V
16 4 -
20
-
24
- ns
tsu
set-up time
CP1 to CP0; CP0 to CP1;
see Figure 8
VCC = 4.5 V
10 3 -
13
-
15
- ns
th hold time CP1 to CP0; CP0 to CP1;
see Figure 8
VCC = 4.5 V
10 6 -
13
-
15
- ns
trec recovery time MR to CP0 and
MR to CP1; see Figure 9
VCC = 4.5 V
5 5 -
5
-
5
- ns
fmax maximum
CP0 or CP1; see Figure 9
frequency
VCC = 4.5 V
30 61 -
24
-
20
- MHz
VCC = 5.0 V;
CL = 15 pF
- 67 -
-
-
-
- MHz
CPD power
VI = GND to VCC 1.5 V; [3] - 36 -
-
-
-
- pF
dissipation
VCC = 5 V; fi = 1 MHz
capacitance
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
74HC_HCT4017
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 3 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
11 of 23
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet 74HCT4017.PDF ] | |
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