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74HC4017 Schematic ( PDF Datasheet ) - NXP

Teilenummer 74HC4017
Beschreibung Johnson decade counter
Hersteller NXP
Logo NXP Logo 



Gesamt 23 Seiten
		
74HC4017 Datasheet, Funktion
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
Rev. 5 — 3 February 2016
Product data sheet
1. General description
The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded
outputs (Q0 to Q9), an output from the most significant flip-flop (Q5-9), two clock inputs
(CP0 and CP1) and an overriding asynchronous master reset input (MR). The counter is
advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or a
HIGH-to-LOW transition at CP1 while CP0 is HIGH. When cascading counters, the Q5-9
output, which is LOW while the counter is in states 5, 6, 7, 8 and 9, can be used to drive
the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0 = Q5-9 =
HIGH; Q1 to Q9 = LOW) independent of the clock inputs (CP0 and CP1). Automatic code
correction of the counter is provided by an internal circuit: following any illegal code the
counter returns to a proper counting mode within 11 clock pulses. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
2. Features and benefits
Wide supply voltage range from 2.0 V to 6.0 V
Input levels:
For 74HC4017: CMOS level
For 74HCT4017: TTL level
Complies with JEDEC standard no. 7 A
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C






74HC4017 Datasheet, Funktion
NXP Semiconductors
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
6. Functional description
Table 3.
MR
H
Function table[1]
CP0
X
LH
L
LL
LX
LH
L
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
= LOW-to-HIGH transition;
= HIGH-to-LOW transition;
7. Limiting values
CP1
X
L
X
H
L
Operation
Q0 = Q5-9 = HIGH;
Q1 to Q9 = LOW
counter advances
counter advances
no change
no change
no change
no change
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
Tamb = 40 C to +125 C
SO16 package
0.5
[1] -
[1] -
-
-
50
65
+7
20
20
25
50
-
+150
V
mA
mA
mA
mA
mA
C
[2] -
500 mW
(T)SSOP16 package
[3] -
500 mW
DHVQFN16 package
[4] -
500 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 8 mW/K above 70 C.
[3] Ptot derates linearly with 5.5 mW/K above 60 C.
[4] Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT4017
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 3 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
6 of 23

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74HC4017 pdf, datenblatt
NXP Semiconductors
11. Waveforms
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
9,
&3LQSXW
*1'
9,
&3LQSXW
*1'
90
WVX WK
90
WVX WK
DDK
Fig 8.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Waveforms showing the set-up and hold times for CP0 to CP1 and CP1 to CP0
9,
&3LQSXW
*1'
9,
&3LQSXW
*1'
9,
05LQSXW
*1'
92+
44
RXWSXW
92/
92+
444
RXWSXW
92/
IPD[
W:
90
IPD[
90
90
W:
WUHF
W:
90
W3+/
90
W3/+
DDK
Fig 9.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Waveforms showing the minimum pulse width for CP0, CP1 and MR input; the maximum frequency for
CP0 and CP1 input; the recovery time for MR and the MR input to Qn and Q5-9 output propagation delays
74HC_HCT4017
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 3 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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