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74HC40105 Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer 74HC40105
Beschreibung 4-bit x 16-word FIFO register
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
74HC40105 Datasheet, Funktion
74HC40105; 74HCT40105
4-bit x 16-word FIFO register
Rev. 4 — 29 January 2016
Product data sheet
1. General description
The 74HC40105; 74HCT40105 is a first-in/first-out (FIFO) "elastic" storage register that
can store 16 4-bit words. It can handle input and output data at different shifting rates.
This feature makes it particularly useful as a buffer between asynchronous systems. Each
word position in the register is clocked by a control flip-flop, which stores a marker bit. A
logic 1 signifies that the data at that position is filled and a logic 0 denotes a vacancy in
that position. The control flip-flop detects the state of the preceding flip-flop and
communicates its own status to the succeeding flip-flop. When a control flip-flop is in the
logic 0 state and sees a logic 1 in the preceding flip-flop, it generates a clock pulse. The
clock pulse transfers data from the preceding four data latches into its own four data
latches and resets the preceding flip-flop to logic 0. The first and last control flip-flops have
buffered outputs. All empty locations "bubble" automatically to the input end, and all valid
data ripples through to the output end. As a result, the status of the first control flip-flop
(data-in ready output - DIR) indicates if the FIFO is full. The status of the last flip-flop
(data-out ready output - DOR) indicates whether the FIFO contains data. As the earliest
data is removed from the bottom of the data stack (output end), all data entered later will
automatically ripple toward the output. Inputs include clamp diodes that enable the use of
current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
Independent asynchronous inputs and outputs
Expandable in either direction
Reset capability
Status indicators on inputs and outputs
3-state outputs
Input levels:
For 74HC40105: CMOS level
For 74HCT40105: TTL level
3-state outputs
Complies with JEDEC standard JESD7A
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C






74HC40105 Datasheet, Funktion
NXP Semiconductors
74HC40105; 74HCT40105
4-bit x 16-word FIFO register
6.2 Data input
Following power-up, the master-reset (MR) input is pulsed HIGH to clear the FIFO
memory (see Figure 7). The data-in-ready flag (DIR = HIGH) indicates that the FIFO input
stage is empty and ready to receive data. When DIR is valid (HIGH), data present at D0 to
D3 can be shifted-in using the SI control input. With SI = HIGH, data is shifted into the
input stage. DIR going LOW provides a busy indication. The data remains at the first
location in the FIFO until DIR is set to HIGH and data moves through the FIFO to the
output stage, or to the last empty location. If the FIFO is not full after the SI pulse, DIR
again becomes valid (HIGH) to indicate that space is available in the FIFO. The DIR flag
remains LOW if the FIFO is full (see Figure 8). To complete the shift-in process, the SI use
must be made LOW. With the FIFO full, SI can be held HIGH until a shift-out (SO) pulse
occurs. Then, following a shift-out of data, an empty location appears at the FIFO input
and DIR goes HIGH to allow the next data to be shifted-in. This data remains at the first
FIFO location until SI goes LOW (see Figure 9).
6.3 Data transfer
After data has been transferred from the input stage of the FIFO following SI = LOW, data
moves through the FIFO asynchronously and is stacked at the output end of the register.
Empty locations appear at the input end of the FIFO as data moves through the device.
6.4 Data output
The data-out-ready flag (DOR = HIGH) indicates that there is valid data at the output (Q0
to Q3). The initial master-reset at power-on (MR = HIGH) sets DOR to LOW (see
Figure 7). After MR = LOW, data shifted into the FIFO moves through to the output stage
causing DOR to go HIGH. As the DOR flag goes HIGH, data can be shifted-out using the
SO = HIGH, data in the output stage is shifted out. DOR going LOW provides a busy
indication. When SO is made LOW, data moves through the FIFO to fill the output stage
and an empty location appears at the input stage. When the output stage is filled DOR
goes HIGH, but if the last of the valid data has been shifted-out leaving the FIFO empty
the DOR flag remains LOW (see Figure 11). With the FIFO empty, the last word that was
shifted-out is latched at the output Q0 to Q3.
With the FIFO empty, the SO input can be held HIGH until the SI control input is used.
Following an SI pulse, data moves through the FIFO to the output stage, resulting in the
DOR flag pulsing HIGH and a shift-out of data occurring. The SO control must be made
LOW before additional data can be shifted-out (see Figure 14).
6.5 High-speed burst mode
Assuming the shift-in/shift-out pulses are not applied until the respective status flags are
valid, it follows that the status flags determine the shift-in/shift-out rates. However, without
the status flags, a high-speed burst can be implemented. In this mode, pulse widths
determine the burst-in/ burst-out rates of the shift-in/shift-out inputs. Burst rates of 35 MHz
can be obtained. Shift pulses can be applied without regard to the status flags but shift-in
pulses that would overflow the storage capacity of the FIFO are not allowed (see
Figure 12 and Figure 13).
74HC_HCT40105
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
6 of 36

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74HC40105 pdf, datenblatt
NXP Semiconductors
74HC40105; 74HCT40105
4-bit x 16-word FIFO register
Table 6. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 18.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
th hold time Dn to SI; see Figure 17
VCC = 2.0 V
125 44 - 155
-
190
- ns
VCC = 4.5 V
25 16 - 31
-
38
- ns
VCC = 6.0 V
21 13 - 26
-
32
- ns
fmax maximum SI, SO using flags or
frequency burst mode; see Figure 8
and Figure 11; see
Figure 12 and Figure 13
VCC = 2.0 V
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
SI, SO cascaded; see
Figure 8 and Figure 11
3.6 10 - 2.8
-
2.4
- MHz
18 30 - 14
-
12
- MHz
- 33 -
-
-
-
- MHz
21 36 - 16
-
14
- MHz
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
CPD power
VI = GND to VCC
dissipation
capacitance
3.6 10 - 2.8
-
2.4
- MHz
18 30 - 14
-
12
- MHz
21 36 - 16
-
14
- MHz
[7] - 134 -
-
-
-
- pF
74HC_HCT40105
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
12 of 36

12 Page





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