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PDF W13NK80Z Data sheet ( Hoja de datos )

Número de pieza W13NK80Z
Descripción STW13NK80Z
Fabricantes STMicroelectronics 
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No Preview Available ! W13NK80Z Hoja de datos, Descripción, Manual

STW13NK80Z
N-channel 800V - 0.53- 12A - TO-247
Zener-protected SuperMESH™ Power MOSFET
General features
Type
STW13NK80Z
VDSS
800V
RDS(on)
<0.65
ID pW
12A 230W
Extremely high dv/dt capability
100% avalanche tested
Gate charge minimized
Very low intrinsic capacitances
t(s)Very good manufacturing repeatibility
ucDescription
rodThe SuperMESH™ series is obtained through an
Pextreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
tepushing on-resistance significantly down, special
lecare is taken to ensure a very good dv/dt
ocapability for the most demanding applications.
bsSuch series complements ST full range of high
voltage MOSFETs including revolutionary
- OMDmesh™ products.
t(s)Applications
ucSwitching application
TO-247
Internal schematic diagram
te ProdOrder codes
olePart number
ObsSTW13NK80Z
Marking
W13NK80Z
Package
TO-247
Packaging
Tube
October 2006
Rev 4
1/14
www.st.com
14

1 page




W13NK80Z pdf
STW13NK80Z
2 Electrical characteristics
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 5. On/off states
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
Drain-source
V(BR)DSS breakdown voltage
ID = 1mA, VGS =0
800
V
IDSS
Zero gate voltage
drain current (VGS = 0)
VDS = max rating
VDS = max rating,
TC = 125°C
1 µA
50 µA
IGSS
Gate-body leakage
current (VDS = 0)
VGS = ± 20V
±10 µA
VGS(th)
t(s)RDS(on)
Gate threshold voltage
Static drain-source on
resistance
VDS = VGS, ID = 100µA
VGS = 10V, ID = 6A
3
3.75 4.5
0.53 0.65
V
ducTable 6.
roSymbol
Dynamic
Parameter
Test conditions
Min. Typ. Max. Unit
te Pgfs (1)
Forward
transconductance
VDS = 15V, ID = 6A
11 S
oleCiss
bsCoss
OCrss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 25V, f = 1MHz,
VGS = 0
3480
312
67
pF
pF
pF
t(s) -Coss
(2)
eq
Equivalent output
capacitance
VGS = 0V, VDS = 0V
to 720V
150 pF
ctd(on)
utr
rodtd(off)
tf
te PQg
Qgs
le Qgd
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 400V, ID = 6A
RG = 4.7VGS = 10V
(see Figure 13)
VDD = 640V, ID = 12A,
VGS = 10V, RG = 4.7
(see Figure 14)
33 ns
22 ns
95 ns
55 ns
115 155 nC
31 nC
51 nC
so 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
b 2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
O increases from 0 to 80% VDSS.
5/14

5 Page





W13NK80Z arduino
STW13NK80Z
4 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
Obsolete Product(s) - Obsolete Product(s)
11/14

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