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HCPL-0500 Schematic ( PDF Datasheet ) - AVAGO

Teilenummer HCPL-0500
Beschreibung High Speed Optocouplers
Hersteller AVAGO
Logo AVAGO Logo 




Gesamt 16 Seiten
HCPL-0500 Datasheet, Funktion
6N135/6, HCNW135/6
HCPL-2502/0500/0501
Single Channel, High Speed Optocouplers
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
These diode-transistor optoc­oup­lers use an insulating
layer between a LED and an integrated photodetector to
provide elec­trical ins­u­lation between input and out­put.
Separate connections for the photodiode bias and out-
put-transistor collector increase the speed up to a hun-
dred times that of a conven­tional phototransistor coupler
by reduci­ng the base-collector capacitance.
These single channel optocoupl­ers are available in
8-Pin DIP­, SO-8 and Widebody package configurations.
The 6N135, HCPL-0500, and HCNW135 are for use in TTL/
CMOS, TTL/LSTTL or wide bandwidth analog applications.
Current transfer ratio (CTR) for these devices is 7% mini-
mum at IF = 16 mA.
The 6N136, HCPL-2502, HCPL-0501, and HCNW136 are
designed for high speed TTL/TTL applications. A standard
16 mA TTL sink current through the input LED will pro-
vide enough output current for 1 TTL load and a 5.6 k
pull-up resistor. CTR for these devices is 19% minimum at
IF = 16 mA.
Functional Diagram
NC 1
ANODE 2
CATHODE 3
NC 4
8 VCC
7 VB
6 VO
5 GND
TRUTH TABLE
(POSITIVE LOGIC)
LED VO
ON LOW
OFF HIGH
Features
High speed: 1 Mb/s
TTL compatible
Available in 8-Pin DIP, SO-8, widebody packages
Open collector output
Safety approval
UL
for
Recognized – 3750
1 minute for HCNW
Varnmds fOorp1tiomnin0u2t0ed(5e0v0ic0eVs)rms
per UL1577
CSA Approved
IEC/EN/DIN EN 60747-5-5 Approved
–––deVVVvIIIOOOiRRRcMMMes===
567 V peak for SO-8 devices
630 V peak for DIP 300 mil devices
1414 V peak for DIP 400 mil (widebody)
Dual channel version available (253X/053X/0534)
Applications
High voltage insulation
Video signal isolation
Line receivers
Feedback element in switched mode power supplies
High speed logic ground isolation
– TTL/TTL, TTL/CMOS, TTL/LSTTL
Replaces pulse transformers
Replaces slow phototransistor isolators
Analog signal ground isolation
A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.






HCPL-0500 Datasheet, Funktion
8-Pin Widebody DIP Package with Gull Wing Surface Mount Option 300 (HCNW135/6)
11.23 ± 0.15
(0.442 ± 0.006)
LAND PATTERN RECOMMENDATION
87 6 5
9.00 ± 0.15
(0.354 ± 0.006)
1234
1.55
(0.061)
MAX.
4.00
(0.158)
MAX.
13.56
(0.534)
1.3
(0.051)
2.29
(0.09)
12.30 ± 0.30
(0.484 ± 0.012)
11.00
(0.433)
MAX.
0.254
+ 0.076
- 0.0051
(0.010
+ 0.003)
- 0.002)
1.80 ± 0.15
(0.071 ± 0.006)
2.54
(0.100)
BSC
0.75 ± 0.25
(0.030 ± 0.010)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
1.00 ± 0.15
(0.039 ± 0.006)
7 ° NOM.
Solder Reflow Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The devices contained in this data sheet have been approved by the following organizations:
UL
CSA
IEC/EN/DIN EN 60747-5-5
Recognized under UL 1577, Component Recognition Program, File E55361.
Approved under CSA Component Acceptance Notice #5, File CA 88324.
(HCNW and Option 060/360/560 only)
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HCPL-0500 pdf, datenblatt
Package Characteristics
Over recommended temperature (TA = 0°C to 70°C) unless otherwise specified.
Parameter
Sym. Device
Min. Typ.* Max. Units
Input-Output
Momentary
Withstand
VISO
8-Pin DIP SO-8
Widebody
3750
5000
Voltage**
8-Pin DIP (Option 020) 5000
II-O 8-Pin DIP
V rms
1 µA
Input-Output
Resistance
RI-O
8-Pin DIP SO-8
Widebody
Input-Output
Capacitance
CI-O
8-Pin DIP SO-8
Widebody
1012 Ω
1012
1013
1011
0.6 pF
0.5 0.6
Test Conditions
RH < 50%,
t = 1 min.,
TA = 25°C
45% RH, t = 5 s,
VTAI-O==235°kCVdc,
VI-O = 500 Vdc
TA = 25°C
TA = 100°C
f = 1 MHz
Fig.
Note
6, 14
6, 15
6, 12, 15
6, 16
6
6
*
**
AThlletyIpnipcuatls-Oaut TtpA u=t2M5°oCm. entary
Withstand
Voltage
is
a
dielectric
voltage
rating
that
should
not
be
interpreted
as
an
input-output
continuous
voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-5 Insulation Related Characteristics Table (if applicable), your
equipment level safety specification or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage,” publication number
5963-2203E.
Notes:
  1.  Derate linearly above 70°C free-air temperature at a rate of 0.8 mA/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 0.5 mA/°C (SO-8).
  2.  Derate linearly above 70°C free-air temperature at a rate of 1.6 mA/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 1.0 mA/°C (SO-8).
  3.  Derate linearly above 70°C free-air temperature at a rate of 0.9 mW/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 1.1 mW/°C (SO-8).
  4.  Derate linearly above 70°C free-air temperature at a rate of 2.0 mW/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 2.3 mW/°C (SO-8).
  5.  CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current, IO, to the forward LED input current, IF, times 100.
  6.  Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
  7.  Common mode transient immunity in a Logic High level is the maximum tolerable (positive) dVCM/dt on the leading edge of the common mode
pulse signal, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 2.0 V). Common mode transient immunity in a Logic Low
level is the maximum tolerable (negative) dVCM/dt on the trailing edge of the common mode pulse signal, VCM, to assure that the output will
remain in a Logic Low state (i.e., VO < 0.8 V).
  8.  The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and the 5.6 kΩ pull-up resistor.
  9.  The 4.1 kΩ load represents 1 LSTTL unit load of 0.36 mA and 6.1 kΩ pull-up resistor.
10.  The frequency at which the ac output voltage is 3 dB below its mid-frequency value.
11.  The JEDEC registration for the 6N136 specifies a minimum CTR of 15%. Avago guarantees a minimum CTR of 19%.
12.  See Option 020 data sheet for more information.
13.  Use of a 0.1 µf bypass capacitor connected between pins 5 and 8 is recommended.
14.  In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 4500 V rms for 1 second (leakage detec-
tion current limit, II-O ≤ 5 µA). This test is performed before the 100% Production test shown in the IEC/EN/DIN EN 60747-5-5 Insulation Related
Characteristics Table if applicable.
15.  In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (leakage detec-
tion current limit, II-O ≤ 5 µA). This test is performed before the 100% Production test shown in the IEC/EN/DIN EN 60747-5-5 Insulation Related
Characteristics Table if applicable.
16.  This rating is equally validated by an equivalent ac proof test.
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